Digital Power Starter Kit 3 Firmware
dsPIC33C Buck Converter Voltage Mode Control Example
dev_buck_pconfig.c
1 /*
2  * File: drv_buck_pconfig.c
3  * Author: M91406
4  *
5  * Created on March 12, 2020, 4:31 PM
6  */
7 
8 #if (__XC16_VERSION__ > 1500)
9  #pragma message ("Warning: Library file '" __FILE__ "' has not been tested with the recently selected compiler version")
10 #endif
11 
12 #include <xc.h> // include processor files - each processor file is guarded.
13 #include <stdint.h> // include standard integer types header file
14 #include <stdbool.h> // include standard boolean types header file
15 
16 #include "dev_buck_pconfig.h"
17 #include "dev_buck_templates.h"
18 
19 /* PRIVATE VARIABLES */
25 volatile uint16_t adcore_mask=0;
26 
32 volatile uint16_t adcore_diff_mask=0;
33 
34 /* PRIVATE FUNCTION CALL PROTOTYPES */
35 
36 volatile uint16_t buckGPIO_PrivateInitialize(volatile struct BUCK_GPIO_INSTANCE_s* buckGPIOInstance);
37 
38 
54 volatile uint16_t buckPWM_ModuleInitialize(volatile struct BUCK_CONVERTER_s* buckInstance)
55 {
56  volatile uint16_t retval=1;
57  volatile struct P33C_PWM_MODULE_s* pwm;
58 
59  // Make sure power to the peripheral is enabled
60  volatile bool _pmdlock = PMDCONbits.PMDLOCK; // Copy state of PMD lock bit
61  PMDCONbits.PMDLOCK = 0; // Unlock PMD register writes
62  PMD1bits.PWMMD = 0; // PWM Module Disable: PWM module is enabled
63  PMDCONbits.PMDLOCK = _pmdlock; // set previous state of PMD lock
64 
65  // DISABLE ALL PWM GENERATORS
66  PG1CONLbits.ON = 0; // PWM Generator #1 Enable: PWM Generator is not enabled
67  PG2CONLbits.ON = 0; // PWM Generator #2 Enable: PWM Generator is not enabled
68  PG3CONLbits.ON = 0; // PWM Generator #3 Enable: PWM Generator is not enabled
69  PG4CONLbits.ON = 0; // PWM Generator #4 Enable: PWM Generator is not enabled
70 
71  #if defined (PG5CONL)
72  PG5CONLbits.ON = 0; // PWM Generator #5 Enable: PWM Generator is not enabled
73  #endif
74  #if defined (PG6CONL)
75  PG6CONLbits.ON = 0; // PWM Generator #6 Enable: PWM Generator is not enabled
76  #endif
77  #if defined (PG7CONL)
78  PG7CONLbits.ON = 0; // PWM Generator #7 Enable: PWM Generator is not enabled
79  #endif
80  #if defined (PG8CONL)
81  PG8CONLbits.ON = 0; // PWM Generator #8 Enable: PWM Generator is not enabled
82  #endif
83 
84  // Write default PWM Module configuration to PWM module base registers
85  pwm = p33c_PwmModule_GetHandle();
86  retval &= p33c_PwmModule_ConfigWrite(buckPwmModuleConfig);
87 
88  // If buck converter has been configured in MASTER PERIOD mode
89  if (buckInstance->sw_node[0].master_period_enable) // If master period mode is enabled...
90  pwm->vMPER.value = buckInstance->sw_node[0].period; // Set Period of phase #1
91 
92  return(retval);
93 }
94 
95 
110 volatile uint16_t buckPWM_ChannelInitialize(volatile struct BUCK_CONVERTER_s* buckInstance)
111 {
112  volatile uint16_t retval=1;
113  volatile uint16_t _i=0;
114 
115  volatile struct P33C_GPIO_INSTANCE_s* gpio;
116  volatile struct P33C_PWM_GENERATOR_s* pg;
117  volatile uint16_t pwm_Instance;
118  volatile uint16_t gpio_Instance;
119 
120  for (_i=0; _i<buckInstance->set_values.no_of_phases; _i++) {
121 
122  // LOAD PERIPHERAL INSTANCES FROM BUCK CONVERTER OBJECT
123  pwm_Instance = buckInstance->sw_node[_i].pwm_instance;
124  gpio_Instance = buckInstance->sw_node[_i].gpio_instance;
125 
126  // CAPTURE MEMORY ADDRESS OF GIVEN PWM GENERATOR INSTANCE
127  gpio = p33c_GpioInstance_GetHandle(gpio_Instance);
128 
129  // WRITE GPIO CONFIGURATION OF PWM OUTPUT(S)
130  gpio->LATx.value &= ~(0x0001 << buckInstance->sw_node[_i].gpio_high); // Clear PWMxH output LOW
131  gpio->LATx.value &= ~(0x0001 << buckInstance->sw_node[_i].gpio_low); // Clear PWMxL output LOW
132  gpio->TRISx.value &= ~(0x0001 << buckInstance->sw_node[_i].gpio_high); // Clear PWMxH output to OUTPUT
133  gpio->TRISx.value &= ~(0x0001 << buckInstance->sw_node[_i].gpio_low); // Clear PWMxL output to OUTPUT
134  gpio->CNPDx.value |= (0x0001 << buckInstance->sw_node[_i].gpio_high); // Enable intern pull down register (PWM1H)
135  gpio->CNPDx.value |= (0x0001 << buckInstance->sw_node[_i].gpio_low); // Enable intern pull down register (PWM1L)
136 
137  // COPY CONFIGURATION FROM TEMPLATE TO PWM GENERATOR x CONTROL REGISTERS
138  pg = p33c_PwmGenerator_GetHandle(pwm_Instance);
139  retval &= p33c_PwmGenerator_ConfigWrite(buckInstance->sw_node[_i].pwm_instance, buckPwmGeneratorConfig);
140 
141  // LOAD PWM GENERATOR TIMING SETTINGS FROM BUCK CONVERTER OBJECT
142  pg->PGxCONH.bits.MPERSEL = (uint16_t)buckInstance->sw_node[_i].master_period_enable;
143  pg->PGxCONL.bits.HREN = (uint16_t)buckInstance->sw_node[_i].high_resolution_enable;
144 
145  pg->PGxDC.value = buckInstance->sw_node[_i].duty_ratio_min; // PGxDC: PWM GENERATOR x DUTY CYCLE REGISTER
146  pg->PGxPER.value = buckInstance->sw_node[_i].period; // PGxPER: PWM GENERATOR x PERIOD REGISTER
147  pg->PGxDTL.value = buckInstance->sw_node[_i].dead_time_falling; // PGxDTL: PWM GENERATOR x DEAD-TIME REGISTER LOW
148  pg->PGxDTH.value = buckInstance->sw_node[_i].dead_time_rising; // PGxDTH: PWM GENERATOR x DEAD-TIME REGISTER HIGH
149  pg->PGxLEBL.value = buckInstance->sw_node[_i].leb_period; // PWM GENERATOR x LEADING-EDGE BLANKING REGISTER LOW
150 
151  // ToDo: PWM Synchronization needs to be more universaL
152  // PWM synchronization only work within groups of 4 (PG1-PG4 or PG5-PG8)
153  // Multiphase boost converter auto PWM phase synchronization
154  if ((_i == 0) && ((uint16_t)(buckInstance->set_values.no_of_phases) > 1U))
155  { // First phase is always master phase
156  pg->PGxCONH.bits.MSTEN = 1; // Enable Master synchronization mode
157  pg->PGxCONH.bits.SOCS = 0b0000; // Master PWM always triggers itself
158  pg->PGxEVTL.bits.PGTRGSEL = 0b011; // PGxTRIGC is always used as PWM synchronization trigger output
159  pg->PGxTRIGC.value = buckInstance->sw_node[_i+1].phase; // Set phase shift between master phase and first synchronized phase
160  pg->PGxCONH.bits.UPDMOD = 0b001; // Immediate update
161  pg->PGxEVTL.bits.UPDTRG = 0b11; // A write of the PGxTRIGA register automatically sets the UPDATE bit
162  }
163  else if ((0 < _i) && (_i < (buckInstance->set_values.no_of_phases-1)))
164  { // Every synchronized phase is synchronized to previous phase while being master to following
165  pg->PGxCONH.bits.MSTEN = 1; // Enable Master synchronization mode
166  pg->PGxCONH.bits.SOCS = buckInstance->sw_node[_i-1].pwm_instance; // synchronized PWM is always triggered by previous generator while providing trigger for following
167  pg->PGxEVTL.bits.PGTRGSEL = 0b011; // PGxTRIGC is always used as PWM synchronization trigger output
168  pg->PGxTRIGC.value = buckInstance->sw_node[_i+1].phase; // Set phase shift between master phase and first synchronized phase
169  pg->PGxCONH.bits.UPDMOD = 0b011; // Sync immediate update
170  pg->PGxEVTL.bits.UPDTRG = 0; // User must set the UPDREQ bit (PGxSTAT[3]) manually
171  }
172  else if ((0 < _i) && (_i == (buckInstance->set_values.no_of_phases-1)))
173  { // Last phase does not provide any master trigger
174  pg->PGxCONH.bits.MSTEN = 0; // Disable Master synchronization mode
175  pg->PGxCONH.bits.SOCS = buckInstance->sw_node[_i-1].pwm_instance; // synchronized PWM is always triggered by previous generator while providing trigger for following
176  pg->PGxEVTL.bits.PGTRGSEL = 0b000; // EOC is the general trigger output
177  pg->PGxTRIGC.value = 0x0000; // Clear phase shift value
178  pg->PGxCONH.bits.UPDMOD = 0b011; // Sync immediate update
179  pg->PGxEVTL.bits.UPDTRG = 0; // User must set the UPDREQ bit (PGxSTAT[3]) manually
180  }
181  else if (buckInstance->set_values.no_of_phases == 1U)
182  { // This is only a single phase system (no PWM dependencies)
183  pg->PGxCONH.bits.MSTEN = 0; // Disable Master synchronization mode
184  pg->PGxCONH.bits.SOCS = 0b0000; // Master PWM always triggers itself
185  pg->PGxEVTL.bits.PGTRGSEL = 0b011; // PGxTRIGC is always used as PWM synchronization trigger output
186  pg->PGxTRIGC.value = 0x0000; // Clear phase shift between master phase and first synchronized phase
187  pg->PGxCONH.bits.UPDMOD = 0b001; // Immediate update
188  pg->PGxEVTL.bits.UPDTRG = 0b11; // A write of the PGxTRIGA register automatically sets the UPDATE bit
189  }
190  else { /* continue */ }
191 
192  // Update PWM generator timing registers
193  pg->PGxSTAT.bits.UPDREQ = 1; // Manually set the Update Request bit
194  pg->PGxCONH.bits.TRGMOD = 1; // all PWM generators are in retriggerable mode
195 
196  }
197 
198  return(retval);
199 }
200 
201 
212 volatile uint16_t buckPWM_Start(volatile struct BUCK_CONVERTER_s* buckInstance)
213 {
214  volatile uint16_t retval=1;
215  volatile uint16_t _i=0;
216  volatile uint16_t timeout=0;
217  volatile uint16_t pwm_Instance=0;
218  volatile uint16_t sync_sw_mask=0;
219  volatile struct P33C_PWM_GENERATOR_s* pg;
220 
221  // Enable all PWM channels of the recent buck converter configuration
222  for(_i=0; _i< buckInstance->set_values.no_of_phases; _i++) {
223 
224  // Capture PWM instance of the recent channel
225  pwm_Instance = buckInstance->sw_node[_i].pwm_instance;
226 
227  // CAPTURE MEMORY ADDRESS OF GIVEN PWM GENERATOR INSTANCE
228  pg = p33c_PwmGenerator_GetHandle(pwm_Instance);
229 
230  pg->PGxIOCONL.value |= P33C_PGxIOCONL_OVREN_SYNC; // PWMxH/L Output Override Enable: PWM generator controls the PWMxH output pin
231  pg->PGxIOCONH.value &= ~(P33C_PGxIOCONH_PEN_SYNC); // PWMxH/L Output Port Disable: PWM generator controls the PWMxH output pin
232 
233  pg->PGxCONL.bits.ON = 1; // PWM Generator Enable: PWM Generator is enabled
234  pg->PGxSTAT.bits.UPDREQ = 1; // Update all PWM timing registers
235 
236  if(pg->PGxCONL.value & P33C_PGxCONL_HRES_EN) // If high resolution is enabled
237  {
238  while((!PCLKCONbits.HRRDY) && (timeout++ < 5000)); // wait for high resolution to get ready
239  if ((timeout >= 5000) || (PCLKCONbits.HRERR)) // if there is an error ...
240  return(0); // ... exit returning ERROR
241  }
242 
243  // Select the control bits for either synchronous or asynchronous PWM drive
244  // note: swapping PWMs changes H/L assignments and the 'active' pin has to
245  // selected in asynchronous mode
246  if (buckInstance->sw_node[_i].sync_drive)
247  sync_sw_mask = P33C_PGxIOCONH_PEN_SYNC;
248  else
249  {
250  if (buckInstance->sw_node[_i].swap_outputs)
251  sync_sw_mask = P33C_PGxIOCONH_PEN_ASYNC_SWAP;
252  else
253  sync_sw_mask = P33C_PGxIOCONH_PEN_ASYNC;
254  }
255 
256  // PWMxH/L Output Port Enable: PWM generator controls the PWMxH output pin
257  pg->PGxIOCONH.value |= sync_sw_mask;
258 
259  // Turn on PWM generator
260  retval &= (volatile uint16_t)(pg->PGxCONL.bits.ON);
261 
262  }
263 
264  return(retval);
265 }
266 
267 
281 volatile uint16_t buckPWM_Stop(volatile struct BUCK_CONVERTER_s* buckInstance)
282 {
283  volatile uint16_t retval=1;
284  volatile uint16_t _i=0;
285  volatile uint16_t pwm_Instance=0;
286  volatile struct P33C_PWM_GENERATOR_s* pg;
287 
288  // Disable all PWM channels of the recent buck converter configuration
289  for(_i=0; _i< buckInstance->set_values.no_of_phases; _i++) {
290 
291  // Capture PWM instance of the recent channel
292  pwm_Instance = buckInstance->sw_node[_i].pwm_instance;
293 
294  // CAPTURE MEMORY ADDRESS OF GIVEN PWM GENERATOR INSTANCE
295  pg = p33c_PwmGenerator_GetHandle(pwm_Instance);
296 
297  pg->PGxIOCONL.value |= P33C_PGxIOCONL_OVREN_SYNC; // PWMxH/L Output Override Enable
298  pg->PGxIOCONH.value &= ~(P33C_PGxIOCONH_PEN_SYNC); // PWMxH/L Output Pint Control Disable
299  pg->PGxCONL.value &= ~(P33C_PGxCONL_PWM_ON); // PWM Generator Disable
300  pg->PGxDC.value = buckInstance->sw_node[_i].duty_ratio_min; // Reset Duty Cycle
301  pg->PGxSTAT.value |= P33C_PGxSTAT_UPDREQ; // Set the Update Request bit to update PWM timing
302 
303  retval &= (volatile uint16_t)((volatile bool)(pg->PGxCONL.bits.ON == 0));
304 
305  }
306 
307  // If defined, reset POWER_GOOD output
308  if(buckInstance->gpio.PowerGood.enabled)
309  retval &= buckGPIO_Clear(&buckInstance->gpio.PowerGood);
310 
311  return(retval);
312 
313 }
314 
315 
327 volatile uint16_t buckPWM_Suspend(volatile struct BUCK_CONVERTER_s* buckInstance)
328 {
329  volatile uint16_t retval=1;
330  volatile uint16_t _i=0;
331  volatile uint16_t pwm_Instance;
332  volatile struct P33C_PWM_GENERATOR_s* pg;
333 
334  // Disable all PWM outputs of the recent buck converter configuration
335  for(_i=0; _i< buckInstance->set_values.no_of_phases; _i++) {
336 
337  // Capture PWM instance of the recent channel
338  pwm_Instance = buckInstance->sw_node[_i].pwm_instance;
339 
340  // CAPTURE MEMORY ADDRESS OF GIVEN PWM GENERATOR INSTANCE
341  pg = p33c_PwmGenerator_GetHandle(pwm_Instance);
342 
343  pg->PGxIOCONL.value |= P33C_PGxIOCONL_OVREN_SYNC; // PWMxH/L Output Override Enable
344  pg->PGxDC.value = 0; // Reset Duty Cycle
345  pg->PGxSTAT.value |= P33C_PGxSTAT_UPDREQ; // Set the Update Request bit to update PWM timing
346 
347  retval &= (bool)(pg->PGxIOCONL.value & P33C_PGxIOCONL_OVREN_SYNC);
348 
349  }
350 
351  // If defined, reset POWER_GOOD output
352  if(buckInstance->gpio.PowerGood.enabled)
353  retval &= buckGPIO_Clear(&buckInstance->gpio.PowerGood);
354 
355  return(retval);
356 
357 }
358 
359 
369 volatile uint16_t buckPWM_Resume(volatile struct BUCK_CONVERTER_s* buckInstance)
370 {
371  volatile uint16_t retval=1;
372  volatile uint16_t _i=0;
373  volatile bool sync_mode=false;
374  volatile uint16_t pwm_Instance=0;
375  volatile uint16_t sync_sw_mask=0;
376  volatile struct P33C_PWM_GENERATOR_s* pg;
377 
378  // Disable all PWM channels of the recent buck converter configuration
379  for(_i=0; _i< buckInstance->set_values.no_of_phases; _i++) {
380 
381  // Capture PWM instance of the recent channel
382  pwm_Instance = (uint16_t)buckInstance->sw_node[_i].pwm_instance;
383 
384  // CAPTURE MEMORY ADDRESS OF GIVEN PWM GENERATOR INSTANCE
385  pg = p33c_PwmGenerator_GetHandle(pwm_Instance);
386 
387  // Select the control bits for either synchronous or asynchronous PWM drive
388  sync_mode = buckInstance->sw_node[_i].sync_drive;
389  sync_mode &= (~buckInstance->status.bits.async_mode);
390 
391  // Select the control bits for either synchronous or asynchronous PWM drive
392  // note: swapping PWMs changes H/L assignments and the 'active' pin has to
393  // selected in asynchronous mode
394  if (sync_mode)
395  { sync_sw_mask = P33C_PGxIOCONL_OVREN_SYNC; }
396  else
397  {
398  if (buckInstance->sw_node[_i].swap_outputs)
399  sync_sw_mask = P33C_PGxIOCONL_OVREN_ASYNC_SWAP;
400  else
401  sync_sw_mask = P33C_PGxIOCONL_OVREN_ASYNC;
402  }
403 
404  // Clear selected override bits
405  pg->PGxSTAT.bits.UPDREQ = 1; // Set the Update Request bit to update PWM timing
406  pg->PGxIOCONL.value &= (volatile uint16_t)(~(sync_sw_mask)); // PWMxH/L Output Override Disable
407 
408  retval &= (uint16_t)((bool)(!(pg->PGxIOCONL.value & sync_sw_mask)));
409 
410  }
411 
412  return(retval);
413 
414 }
415 
416 
429 volatile uint16_t buckADC_ModuleInitialize(void)
430 {
431  volatile uint16_t retval=1;
432 
433  // Make sure power to peripheral is enabled
434  volatile bool _pmdlock = PMDCONbits.PMDLOCK; // Copy state of PMD lock bit
435  PMDCONbits.PMDLOCK = 0; // Unlock PMD register writes
436  PMD1bits.ADC1MD = 0; // ADC Module Power Disable: ADC module power is enabled
437  PMDCONbits.PMDLOCK = _pmdlock; // set previous state of PMD lock
438 
439  // ADCON1L: ADC CONTROL REGISTER 1 LOW
440  ADCON1Lbits.ADON = 0; // ADC Enable: ADC module is off during configuration
441  ADCON1Lbits.ADSIDL = 0; // ADC Stop in Idle Mode: Continues module operation in Idle mode
442 
443  // ADCON1H: ADC CONTROL REGISTER 1 HIGH
444  ADCON1Hbits.SHRRES = 0b11; // Shared ADC Core Resolution Selection: 12-bit resolution ADC resolution = 12-bit (0...4095 ticks)
445  ADCON1Hbits.FORM = 0; // Fractional Data Output Format: Integer
446 
447  // ADCON2L: ADC CONTROL REGISTER 2 LOW
448  ADCON2Lbits.REFCIE = 0;; // Band Gap and Reference Voltage Ready Common Interrupt Enable: Common interrupt is disabled for the band gap ready event
449  ADCON2Lbits.REFERCIE = 0; // Band Gap or Reference Voltage Error Common Interrupt Enable: Disabled
450  ADCON2Lbits.EIEN = 1; // Early Interrupts Enable: The early interrupt feature is enabled
451  ADCON2Lbits.SHREISEL = 0b111; // Shared Core Early Interrupt Time Selection: Early interrupt is set and interrupt is generated 8 TADCORE clocks prior to when the data are ready
452  ADCON2Lbits.SHRADCS = 0b0000001; // Shared ADC Core Input Clock Divider: 2:1 (minimum)
453 
454  // ADCON2H: ADC CONTROL REGISTER 2 HIGH
455  ADCON2Hbits.SHRSAMC = 8; // Shared ADC Core Sample Time Selection: 8x TADs sampling time
456  ADCON2Hbits.REFERR = 0; // reset error flag
457  ADCON2Hbits.REFRDY = 0; // reset bandgap status bit
458 
459  // ADCON3L: ADC CONTROL REGISTER 3 LOW
460  ADCON3Lbits.REFSEL = 0b000; // ADC Reference Voltage Selection: AVDD-toAVSS
461  ADCON3Lbits.SUSPEND = 0; // All ADC Core Triggers Disable: All ADC cores can be triggered
462  ADCON3Lbits.SUSPCIE = 0; // Suspend All ADC Cores Common Interrupt Enable: Common interrupt is not generated for suspend ADC cores
463  ADCON3Lbits.SUSPRDY = 0; // All ADC Cores Suspended Flag: ADC cores have previous conversions in progress
464  ADCON3Lbits.SHRSAMP = 0; // Shared ADC Core Sampling Direct Control: use hardware trigger
465  ADCON3Lbits.CNVRTCH = 0; // Software Individual Channel Conversion Trigger: Next individual channel conversion trigger can be generated (not used)
466  ADCON3Lbits.SWLCTRG = 0; // Software Level-Sensitive Common Trigger: No software, level-sensitive common triggers are generated (not used)
467  ADCON3Lbits.SWCTRG = 0; // Software Common Trigger: Ready to generate the next software common trigger (not used)
468  ADCON3Lbits.CNVCHSEL = 0; // Channel Number Selection for Software Individual Channel Conversion Trigger: AN0 (not used)
469 
470  // ADCON3H: ADC CONTROL REGISTER 3 HIGH
471  ADCON3Hbits.CLKSEL = 0b01; // ADC Module Clock Source Selection: AVCODIV
472  ADCON3Hbits.CLKDIV = 0b000000; // ADC Module Clock Source Divider: 1 Source Clock Period
473  ADCON3Hbits.SHREN = 0; // Shared ADC Core Enable: Shared ADC core is disabled
474  ADCON3Hbits.C0EN = 0; // Dedicated ADC Core 0 Enable: Dedicated ADC Core 0 is disabled
475  ADCON3Hbits.C1EN = 0; // Dedicated ADC Core 1 Enable: Dedicated ADC Core 1 is disabled
476 
477  // ADCON4L: ADC CONTROL REGISTER 4 LOW
478  ADCON4Lbits.SAMC0EN = 0; // Dedicated ADC Core 0 Conversion Delay Enable: Immediate conversion
479  ADCON4Lbits.SAMC1EN = 0; // Dedicated ADC Core 1 Conversion Delay Enable: Immediate conversion
480 
481  // ADCON4H: ADC CONTROL REGISTER 4 HIGH
482  ADCON4Hbits.C0CHS = 0b00; // Dedicated ADC Core 0 Input Channel Selection: AN0
483  ADCON4Hbits.C1CHS = 0b00; // Dedicated ADC Core 1 Input Channel Selection: AN1
484 
485  // ADCON5L: ADC CONTROL REGISTER 5 LOW
486  // ADCON5Lbits.SHRRDY: Shared ADC Core Ready Flag (read only)
487  // ADCON5Lbits.C0RDY: Dedicated ADC Core 0 Ready Flag (read only)
488  // ADCON5Lbits.C1RDY: Dedicated ADC Core 1 Ready Flag (read only)
489  ADCON5Lbits.SHRPWR = 0; // Shared ADC Core Power Enable: ADC core is off
490  ADCON5Lbits.C0PWR = 0; // Dedicated ADC Core 0 Power Enable: ADC core is off
491  ADCON5Lbits.C1PWR = 0; // Dedicated ADC Core 1 Power Enable: ADC core is off
492 
493  // ADCON5H: ADC CONTROL REGISTER 5 HIGH
494  ADCON5Hbits.WARMTIME = 0b1111; // ADC Dedicated Core x Power-up Delay: 32768 Source Clock Periods
495  ADCON5Hbits.SHRCIE = 0; // Shared ADC Core Ready Common Interrupt Enable: Common interrupt is disabled for an ADC core ready event
496  ADCON5Hbits.C0CIE = 0; // C1CIE: Dedicated ADC Core 0 Ready Common Interrupt Enable: Common interrupt is disabled
497  ADCON5Hbits.C1CIE = 0; // C1CIE: Dedicated ADC Core 1 Ready Common Interrupt Enable: Common interrupt is disabled
498 
499  // ADCORExL: DEDICATED ADC CORE x CONTROL REGISTER LOW
500  ADCORE1Lbits.SAMC = 0b0000000000; // Dedicated ADC Core 1 Conversion Delay Selection: 2 TADCORE (minimum)
501  ADCORE0Lbits.SAMC = 0b0000000000; // Dedicated ADC Core 0 Conversion Delay Selection: 2 TADCORE (minimum)
502 
503  // ADCORExH: DEDICATED ADC CORE x CONTROL REGISTER HIGH
504  ADCORE0Hbits.RES = 0b11; // ADC Core x Resolution Selection: 12 bit
505  ADCORE0Hbits.ADCS = 0b0000000; // ADC Core x Input Clock Divider: 2 Source Clock Periods
506  ADCORE0Hbits.EISEL = 0b111; // Early interrupt is set and an interrupt is generated 8 TADCORE clocks prior
507 
508  ADCORE1Hbits.RES = 0b11; // ADC Core x Resolution Selection: 12 bit
509  ADCORE1Hbits.ADCS = 0b0000000; // ADC Core x Input Clock Divider: 2 Source Clock Periods
510  ADCORE1Hbits.EISEL = 0b111; // Early interrupt is set and an interrupt is generated 8 TADCORE clocks prior
511 
512  return(retval);
513 
514 }
515 
516 
528 volatile uint16_t buckADC_ChannelInitialize(volatile struct BUCK_ADC_INPUT_SETTINGS_s* adcInstance)
529 {
530  volatile uint16_t retval=1;
531  volatile uint8_t* ptrADCRegister;
532  volatile uint8_t bit_offset;
533 
534  // Initialize ADC input registers
535  if (adcInstance->enabled) {
536 
537  // Write level trigger setting
538  if (adcInstance->adc_input < 16) {
539  ADLVLTRGL |= ((uint16_t)(adcInstance->level_trigger) << adcInstance->adc_input);
540  ADEIEL |= ((uint16_t)(adcInstance->early_interrupt_enable) << adcInstance->adc_input);
541  ADIEL |= ((uint16_t)(adcInstance->interrupt_enable) << adcInstance->adc_input);
542  }
543  else if (adcInstance->adc_input < 32) {
544  ADLVLTRGH |= ((uint16_t)(adcInstance->level_trigger) << (adcInstance->adc_input - 16));
545  ADEIEH |= ((uint16_t)(adcInstance->early_interrupt_enable) << (adcInstance->adc_input - 16));
546  ADIEH |= ((uint16_t)(adcInstance->interrupt_enable) << (adcInstance->adc_input - 16));
547  }
548  else {
549  return(0); // ADC input number out of range
550  }
551 
552  // write input mode setting
553  if (adcInstance->adc_input < 8)
554  bit_offset = (2 * adcInstance->adc_input);
555  else if (adcInstance->adc_input < 16)
556  bit_offset = (2 * (adcInstance->adc_input-8));
557  else if (adcInstance->adc_input < 24)
558  bit_offset = (2 * (adcInstance->adc_input-16));
559  else if (adcInstance->adc_input < 32)
560  bit_offset = (2 * (adcInstance->adc_input-24));
561  else
562  return(0); // ADC input number out of range
563 
564  ptrADCRegister = (volatile uint8_t *)
565  ((volatile uint8_t *)&ADMOD0L + (volatile uint8_t)(adcInstance->adc_input >> 8));
566 
567  *ptrADCRegister |= ((unsigned int)adcInstance->signed_result << bit_offset);
568  *ptrADCRegister |= ((unsigned int)adcInstance->differential_input << (bit_offset + 1));
569 
570  // Write ADC trigger source setting
571  ptrADCRegister = (volatile uint8_t *)
572  ((volatile uint8_t *)&ADTRIG0L + (volatile uint8_t)adcInstance->adc_input);
573 
574  *ptrADCRegister = (volatile uint8_t)adcInstance->trigger_source;
575 
576  // Register ADC core to be active
577  switch (adcInstance->adc_core) {
578  case 0:
579  adcore_mask |= ADC_CORE0_MASK_INDEX;
580  if (adcInstance->differential_input)
581  adcore_diff_mask |= ADC_CORE0_MASK_INDEX;
582  break;
583  case 1:
584  adcore_mask |= ADC_CORE1_MASK_INDEX;
585  if (adcInstance->differential_input)
586  adcore_diff_mask |= ADC_CORE1_MASK_INDEX;
587  break;
588  case 2:
589  adcore_mask |= ADC_CORE2_MASK_INDEX;
590  if (adcInstance->differential_input)
591  adcore_diff_mask |= ADC_CORE2_MASK_INDEX;
592  break;
593  case 3:
594  adcore_mask |= ADC_CORE3_MASK_INDEX;
595  if (adcInstance->differential_input)
596  adcore_diff_mask |= ADC_CORE3_MASK_INDEX;
597  break;
598  default:
599  adcore_mask |= ADC_SHRCORE_MASK_INDEX;
600  if (adcInstance->differential_input)
601  adcore_diff_mask |= ADC_SHRCORE_MASK_INDEX;
602  break;
603  }
604 
605  }
606 
607  return(retval);
608 
609 }
610 
611 
622 volatile uint16_t buckADC_Start(void)
623 {
624  volatile uint16_t retval=1;
625  volatile uint16_t timeout=0;
626  volatile uint16_t adcore_mask_compare=0;
627 
628  // Turn on ADC module
629  ADCON1Lbits.ADON = 1;
630 
631  ADCON5L = adcore_mask; // Enable power to all used ADC cores
632  adcore_mask_compare = ((adcore_mask << 8) | adcore_mask); // Set ADC Core Ready Bit Mask
633 
634  while ((ADCON5L != adcore_mask_compare) & (timeout++ < ADC_POWERUP_TIMEOUT)); // Wait until ADC cores are ready
635  if (timeout >= ADC_POWERUP_TIMEOUT) return(0); // Skip if powering up ADC cores was unsuccessful
636  ADCON3H = adcore_mask; // Enable ADC cores
637 
638 
639  return(retval);
640 
641 }
642 
643 
653 volatile uint16_t buckGPIO_Set(volatile struct BUCK_GPIO_INSTANCE_s* buckGPIOInstance)
654 {
655  volatile uint16_t retval=1;
656  volatile uint16_t filter_mask=0;
657  volatile struct P33C_GPIO_INSTANCE_s* gpio;
658 
659  // Capture register of GPIO port
660  gpio = p33c_GpioInstance_GetHandle(buckGPIOInstance->port);
661 
662  // Capture filter mask
663  filter_mask = (0x0001 << buckGPIOInstance->pin);
664 
665  // Set pin to ACTIVE state
666  if (buckGPIOInstance->polarity == 0)
667  gpio->LATx.value |= (filter_mask); // Set pin bit in register
668  else
669  gpio->LATx.value &= ~(filter_mask); // Clear pin bit in register
670 
671  // Verifying the set state is applied at the pin
672  retval = (bool)((gpio->LATx.value & filter_mask) == (gpio->PORTx.value & filter_mask));
673 
674  return(retval);
675 
676 }
677 
678 
688 volatile uint16_t buckGPIO_Clear(volatile struct BUCK_GPIO_INSTANCE_s* buckGPIOInstance)
689 {
690  volatile uint16_t retval=1;
691  volatile uint16_t filter_mask=0;
692  volatile struct P33C_GPIO_INSTANCE_s* gpio;
693 
694  // Capture register of GPIO port
695  gpio = p33c_GpioInstance_GetHandle(buckGPIOInstance->port);
696 
697  // Capture filter mask
698  filter_mask = (0x0001 << buckGPIOInstance->pin);
699 
700  // Set pin to INACTIVE state
701  if (buckGPIOInstance->polarity == 0)
702  gpio->LATx.value &= ~(filter_mask); // Clear pin bit in register
703  else
704  gpio->LATx.value |= (filter_mask); // Set pin bit in register
705 
706  // Verifying the set state is applied at the pin
707  retval = (bool)((gpio->LATx.value & filter_mask) == (gpio->PORTx.value & filter_mask));
708 
709  return(retval);
710 
711 }
712 
713 
723 volatile bool buckGPIO_GetPinState(volatile struct BUCK_GPIO_INSTANCE_s* buckGPIOInstance)
724 {
725  volatile bool retval=1;
726  volatile P33C_GPIO_INSTANCE_t* gpio;
727 
728  // Capture register of GPIO port
729  gpio = p33c_GpioInstance_GetHandle(buckGPIOInstance->port);
730 
731  // Read pin
732  retval = (bool)(gpio->PORTx.value & (0x0001 << buckGPIOInstance->pin));
733 
734  // If polarity is inverted (ACTIVE LOW), invert result
735  if(buckGPIOInstance->polarity == 1)
736  retval = (1-retval);
737 
738  return(retval);
739 
740 }
741 
742 
743 
754 volatile uint16_t buckGPIO_Initialize(volatile struct BUCK_CONVERTER_s* buckInstance)
755 {
756  volatile uint16_t retval=1;
757 
758  // Initialize ENABLE input pin
759  if(buckInstance->gpio.EnableInput.enabled)
760  retval = buckGPIO_PrivateInitialize(&buckInstance->gpio.EnableInput);
761 
762  // Initialize POWER GOOD output pin
763  if(buckInstance->gpio.PowerGood.enabled)
764  retval = buckGPIO_PrivateInitialize(&buckInstance->gpio.PowerGood);
765 
766  // If defined, reset POWER_GOOD output
767  if(buckInstance->gpio.PowerGood.enabled)
768  retval &= buckGPIO_Clear(&buckInstance->gpio.PowerGood);
769 
770  return(retval);
771 
772 }
773 
774 
775 
786 volatile uint16_t buckGPIO_PrivateInitialize(volatile struct BUCK_GPIO_INSTANCE_s* buckGPIOInstance)
787 {
788  volatile uint16_t retval=1;
789  volatile struct P33C_GPIO_INSTANCE_s* gpio;
790 
791  // Capture register of GPIO port
792  gpio = p33c_GpioInstance_GetHandle(buckGPIOInstance->port);
793 
794  // Set pin to INACTIVE state
795  if (buckGPIOInstance->polarity == 0)
796  gpio->LATx.value &= ~(0x0001 << buckGPIOInstance->pin); // Clear pin bit in register
797  else
798  gpio->LATx.value |= (0x0001 << buckGPIOInstance->pin); // Set pin bit in register
799 
800  // Set INPUT or OUTPUT in TRIS register
801  if(buckGPIOInstance->io_type == 1)
802  gpio->TRISx.value |= (0x0001 << buckGPIOInstance->pin); // Set pin bit in register
803  else
804  gpio->TRISx.value &= ~(0x0001 << buckGPIOInstance->pin); // Clear pin bit in register
805 
806  // Set Pin in Open Drain Configuration
807  if(buckGPIOInstance->io_type == 2)
808  gpio->ODCx.value |= (0x0001 << buckGPIOInstance->pin); // Set pin bit in register
809  else
810  gpio->ODCx.value &= ~(0x0001 << buckGPIOInstance->pin); // Clear pin bit in register
811 
812  // Set pin as DIGITAL IO
813  gpio->ANSELx.value &= ~(0x0001 << buckGPIOInstance->pin); // Clear pin bit in register
814 
815  // ToDo: Enable register value testing to validate function result
816  retval = 1;
817 
818  return(retval);
819 }
820 
821 // end of file
P33C_GPIO_INSTANCE_s::CNPDx
union P33C_GPIO_INSTANCE_s::@6 CNPDx
BUCK_CONVERTER_STATUS_s::async_mode
volatile bool async_mode
Bit #9: Control bit suspending the synchronous rectifier switch PWM channel.
Definition: dev_buck_typedef.h:218
ADC_POWERUP_TIMEOUT
#define ADC_POWERUP_TIMEOUT
Digital-To-Analog Converter and High Speed Comparator Special Function Register Set.
Definition: dev_buck_ptemp_adc.h:51
BUCK_ADC_INPUT_SETTINGS_s::differential_input
volatile bool differential_input
input channel differential mode enable bit
Definition: dev_buck_typedef.h:435
BUCK_ADC_INPUT_SETTINGS_s::interrupt_enable
volatile bool interrupt_enable
input channel interrupt enable bit
Definition: dev_buck_typedef.h:433
ADC_CORE3_MASK_INDEX
#define ADC_CORE3_MASK_INDEX
This define masks core 3 of ADC.
Definition: dev_buck_ptemp_adc.h:83
P33C_PWM_GENERATOR_s::bits
struct tagPG1CONLBITS bits
Definition: p33c_pwm.h:197
ADC_SHRCORE_MASK_INDEX
#define ADC_SHRCORE_MASK_INDEX
This define masks shared core of ADC.
Definition: dev_buck_ptemp_adc.h:89
BUCK_SWITCH_NODE_SETTINGS_s::gpio_high
volatile uint16_t gpio_high
GPIO port pin-number of PWMxH of the selected PWM generator.
Definition: dev_buck_typedef.h:379
buckADC_ModuleInitialize
volatile uint16_t buckADC_ModuleInitialize(void)
This fucntion initializes the buck by resetting all its registers to default.
Definition: dev_buck_pconfig.c:429
BUCK_SWITCH_NODE_SETTINGS_s::dead_time_rising
volatile uint16_t dead_time_rising
Dead time setting at rising edge of a half-bridge drive.
Definition: dev_buck_typedef.h:390
P33C_PWM_GENERATOR_s::PGxIOCONH
union P33C_PWM_GENERATOR_s::@58 PGxIOCONH
P33C_GPIO_INSTANCE_s::ANSELx
union P33C_GPIO_INSTANCE_s::@0 ANSELx
BUCK_SWITCH_NODE_SETTINGS_s::swap_outputs
volatile bool swap_outputs
Selecting if PWMxH (default) or PWMxL should be the leading PWM output.
Definition: dev_buck_typedef.h:381
P33C_PWM_GENERATOR_s::PGxSTAT
union P33C_PWM_GENERATOR_s::@56 PGxSTAT
p33c_PwmGenerator_ConfigWrite
volatile uint16_t p33c_PwmGenerator_ConfigWrite(volatile uint16_t pgInstance, volatile struct P33C_PWM_GENERATOR_s pgConfig)
Disposes a given PWM generator by resetting all its registers to default.
Definition: p33c_pwm.c:217
P33C_GPIO_INSTANCE_s::LATx
union P33C_GPIO_INSTANCE_s::@3 LATx
buckGPIO_Clear
volatile uint16_t buckGPIO_Clear(volatile struct BUCK_GPIO_INSTANCE_s *buckGPIOInstance)
This function clears the selected general purpose input/output pin.
Definition: dev_buck_pconfig.c:688
p33c_PwmModule_ConfigWrite
volatile uint16_t p33c_PwmModule_ConfigWrite(volatile struct P33C_PWM_MODULE_s pwmConfig)
Writes a user-defined configuration to the PWM base module registers.
Definition: p33c_pwm.c:158
P33C_PWM_GENERATOR_s::PGxDTL
union P33C_PWM_GENERATOR_s::@78 PGxDTL
buckPWM_Suspend
volatile uint16_t buckPWM_Suspend(volatile struct BUCK_CONVERTER_s *buckInstance)
This function disables the PWM generator IOs.
Definition: dev_buck_pconfig.c:327
BUCK_GPIO_INSTANCE_s::io_type
volatile uint16_t io_type
Input/Output definition (0=push-pull output, 1=input, 2=open-drain output)
Definition: dev_buck_typedef.h:476
P33C_PGxSTAT_UPDREQ
#define P33C_PGxSTAT_UPDREQ
Control bit in PGxSTAT setting the Update Request bit.
Definition: dev_buck_ptemp_pwm.h:471
BUCK_CONVERTER_s::status
volatile struct BUCK_CONVERTER_STATUS_s status
BUCK operation status bits.
Definition: dev_buck_typedef.h:502
BUCK_ADC_INPUT_SETTINGS_s::adc_core
volatile uint8_t adc_core
number of the ADC core connected to the selected channel
Definition: dev_buck_typedef.h:431
BUCK_SWITCH_NODE_SETTINGS_s::gpio_instance
volatile uint16_t gpio_instance
GPIO instance of the selected PWM generator.
Definition: dev_buck_typedef.h:378
BUCK_SWITCH_NODE_SETTINGS_s::gpio_low
volatile uint16_t gpio_low
GPIO port pin-number of PWMxL of the selected PWM generator.
Definition: dev_buck_typedef.h:380
BUCK_ADC_INPUT_SETTINGS_s::trigger_source
volatile uint8_t trigger_source
input channel trigger source
Definition: dev_buck_typedef.h:432
p33c_PwmModule_GetHandle
volatile struct P33C_PWM_MODULE_s * p33c_PwmModule_GetHandle(void)
Gets pointer to PWM module SFR set.
Definition: p33c_pwm.c:74
BUCK_SWITCH_NODE_SETTINGS_s::duty_ratio_min
volatile uint16_t duty_ratio_min
Absolute duty cycle minimum during normal operation.
Definition: dev_buck_typedef.h:388
ADC_CORE0_MASK_INDEX
#define ADC_CORE0_MASK_INDEX
This define masks core 0 of ADC.
Definition: dev_buck_ptemp_adc.h:65
P33C_PGxCONL_PWM_ON
#define P33C_PGxCONL_PWM_ON
control bit in PGxCONL enabling/disabling the PWM generator
Definition: dev_buck_ptemp_pwm.h:439
P33C_GPIO_INSTANCE_s::value
volatile uint16_t value
Definition: p33c_gpio.h:54
P33C_PWM_GENERATOR_s
Definition: p33c_pwm.h:195
BUCK_ADC_INPUT_SETTINGS_s
ADC input channel configuration.
Definition: dev_buck_typedef.h:425
BUCK_ADC_INPUT_SETTINGS_s::enabled
volatile bool enabled
input channel enable bit
Definition: dev_buck_typedef.h:427
p33c_PwmGenerator_GetHandle
volatile struct P33C_PWM_GENERATOR_s * p33c_PwmGenerator_GetHandle(volatile uint16_t pgInstance)
Returns the PWM generator index.
Definition: p33c_pwm.c:555
P33C_PWM_GENERATOR_s::PGxLEBL
union P33C_PWM_GENERATOR_s::@69 PGxLEBL
BUCK_SWITCH_NODE_SETTINGS_s::sync_drive
volatile bool sync_drive
Selecting if switch node is driven in synchronous or asnchronous mode.
Definition: dev_buck_typedef.h:384
P33C_PGxIOCONH_PEN_ASYNC_SWAP
#define P33C_PGxIOCONH_PEN_ASYNC_SWAP
Definition: dev_buck_ptemp_pwm.h:466
P33C_PGxIOCONH_PEN_ASYNC
#define P33C_PGxIOCONH_PEN_ASYNC
Definition: dev_buck_ptemp_pwm.h:465
BUCK_GPIO_INSTANCE_s::polarity
volatile uint16_t polarity
Output polarity, where 0=ACTIVE HIGH, 1=ACTIVE_LOW.
Definition: dev_buck_typedef.h:475
P33C_PWM_MODULE_s
Definition: p33c_pwm.h:86
P33C_PWM_GENERATOR_s::value
uint16_t value
Definition: p33c_pwm.h:198
P33C_PGxIOCONL_OVREN_SYNC
#define P33C_PGxIOCONL_OVREN_SYNC
control bits in PGxIOCONL enabling/disabling the PWM output override in synchronous mode
Definition: dev_buck_ptemp_pwm.h:449
P33C_PWM_MODULE_s::value
uint16_t value
Definition: p33c_pwm.h:90
BUCK_ADC_INPUT_SETTINGS_s::adc_input
volatile uint8_t adc_input
number of the ADC input channel used
Definition: dev_buck_typedef.h:430
BUCK_ADC_INPUT_SETTINGS_s::level_trigger
volatile bool level_trigger
input channel level trigger mode enable bit
Definition: dev_buck_typedef.h:437
BUCK_SWITCH_NODE_SETTINGS_s::pwm_instance
volatile uint16_t pwm_instance
number of the PWM channel used
Definition: dev_buck_typedef.h:377
p33c_GpioInstance_GetHandle
volatile struct P33C_GPIO_INSTANCE_s * p33c_GpioInstance_GetHandle(volatile uint16_t gpioInstance)
Gets pointer to GPIO Instance SFR set.
Definition: p33c_gpio.c:45
buckADC_ChannelInitialize
volatile uint16_t buckADC_ChannelInitialize(volatile struct BUCK_ADC_INPUT_SETTINGS_s *adcInstance)
This function initializes the settings for the ADC channel.
Definition: dev_buck_pconfig.c:528
P33C_GPIO_INSTANCE_s::TRISx
union P33C_GPIO_INSTANCE_s::@1 TRISx
ADC_CORE1_MASK_INDEX
#define ADC_CORE1_MASK_INDEX
This define masks core 1 of ADC.
Definition: dev_buck_ptemp_adc.h:71
buckPWM_Start
volatile uint16_t buckPWM_Start(volatile struct BUCK_CONVERTER_s *buckInstance)
This function enables the buck PWM operation.
Definition: dev_buck_pconfig.c:212
BUCK_GPIO_INSTANCE_s::enabled
volatile bool enabled
Specifies, if this IO is used or not.
Definition: dev_buck_typedef.h:472
P33C_PWM_GENERATOR_s::PGxDTH
union P33C_PWM_GENERATOR_s::@79 PGxDTH
P33C_GPIO_INSTANCE_s
Definition: p33c_gpio.h:51
BUCK_SWITCH_NODE_SETTINGS_s::phase
volatile uint16_t phase
Switching signal phase-shift.
Definition: dev_buck_typedef.h:386
BUCK_CONVERTER_s::sw_node
volatile struct BUCK_SWITCH_NODE_SETTINGS_s sw_node[BUCK_MPHASE_COUNT]
BUCK converter switch node settings.
Definition: dev_buck_typedef.h:509
BUCK_GPIO_SETTINGS_s::EnableInput
volatile struct BUCK_GPIO_INSTANCE_s EnableInput
External ENABLE input.
Definition: dev_buck_typedef.h:489
buckGPIO_GetPinState
volatile bool buckGPIO_GetPinState(volatile struct BUCK_GPIO_INSTANCE_s *buckGPIOInstance)
This function gets the state of the selected pin.
Definition: dev_buck_pconfig.c:723
ADC_CORE2_MASK_INDEX
#define ADC_CORE2_MASK_INDEX
This define masks core 2 of ADC.
Definition: dev_buck_ptemp_adc.h:77
BUCK_GPIO_INSTANCE_s::port
volatile uint16_t port
GPIO port instance number (0=Port RA, 0=Port RB, 0=Port RC, etc.)
Definition: dev_buck_typedef.h:473
buckPWM_Stop
volatile uint16_t buckPWM_Stop(volatile struct BUCK_CONVERTER_s *buckInstance)
This function stops the buck PWM output.
Definition: dev_buck_pconfig.c:281
P33C_PGxCONL_HRES_EN
#define P33C_PGxCONL_HRES_EN
control bit in PGxCONL enabling/disabling High Resolution Mode
Definition: dev_buck_ptemp_pwm.h:444
BUCK_CONVERTER_s::gpio
volatile struct BUCK_GPIO_SETTINGS_s gpio
BUCK converter additional GPIO specification.
Definition: dev_buck_typedef.h:510
P33C_PWM_GENERATOR_s::PGxCONH
union P33C_PWM_GENERATOR_s::@55 PGxCONH
buckPwmGeneratorConfig
volatile struct P33C_PWM_GENERATOR_s buckPwmGeneratorConfig
PWM generator default configuration.
Definition: dev_buck_ptemp_pwm.c:47
P33C_GPIO_INSTANCE_s::PORTx
union P33C_GPIO_INSTANCE_s::@2 PORTx
P33C_PWM_GENERATOR_s::PGxPER
union P33C_PWM_GENERATOR_s::@74 PGxPER
buckGPIO_Initialize
volatile uint16_t buckGPIO_Initialize(volatile struct BUCK_CONVERTER_s *buckInstance)
This function initializes the buck input pins.
Definition: dev_buck_pconfig.c:754
buckPwmModuleConfig
volatile struct P33C_PWM_MODULE_s buckPwmModuleConfig
PWM module default configuration.
Definition: dev_buck_ptemp_pwm.c:16
buckGPIO_PrivateInitialize
volatile uint16_t buckGPIO_PrivateInitialize(volatile struct BUCK_GPIO_INSTANCE_s *buckGPIOInstance)
This function sets the pin as input or output.
Definition: dev_buck_pconfig.c:786
buckPWM_Resume
volatile uint16_t buckPWM_Resume(volatile struct BUCK_CONVERTER_s *buckInstance)
This function resumes the buck PWM operation.
Definition: dev_buck_pconfig.c:369
BUCK_CONVERTER_s::set_values
volatile struct BUCK_CONVERTER_SETTINGS_s set_values
Control field for global access to references.
Definition: dev_buck_typedef.h:505
BUCK_GPIO_INSTANCE_s::pin
volatile uint16_t pin
GPIO port pin number.
Definition: dev_buck_typedef.h:474
BUCK_GPIO_SETTINGS_s::PowerGood
volatile struct BUCK_GPIO_INSTANCE_s PowerGood
Power Good Output.
Definition: dev_buck_typedef.h:490
P33C_PWM_GENERATOR_s::PGxEVTL
union P33C_PWM_GENERATOR_s::@59 PGxEVTL
BUCK_SWITCH_NODE_SETTINGS_s::master_period_enable
volatile bool master_period_enable
Selecting MASTER or Individual period register.
Definition: dev_buck_typedef.h:382
BUCK_SWITCH_NODE_SETTINGS_s::leb_period
volatile uint16_t leb_period
Leading-Edge Blanking period.
Definition: dev_buck_typedef.h:392
P33C_PWM_GENERATOR_s::PGxCONL
union P33C_PWM_GENERATOR_s::@54 PGxCONL
BUCK_ADC_INPUT_SETTINGS_s::early_interrupt_enable
volatile bool early_interrupt_enable
input channel early interrupt enable bit
Definition: dev_buck_typedef.h:434
buckPWM_ModuleInitialize
volatile uint16_t buckPWM_ModuleInitialize(volatile struct BUCK_CONVERTER_s *buckInstance)
Initializes the buck PWM module by resetting its registers to default.
Definition: dev_buck_pconfig.c:54
P33C_PWM_GENERATOR_s::PGxTRIGC
union P33C_PWM_GENERATOR_s::@77 PGxTRIGC
P33C_PGxIOCONH_PEN_SYNC
#define P33C_PGxIOCONH_PEN_SYNC
control bits in PGxIOCONH enabling/disabling the PWM outputs in synchronous mode
buckADC_Start
volatile uint16_t buckADC_Start(void)
This function enables the ADC module and starts the ADC cores analog inputs for the required input si...
Definition: dev_buck_pconfig.c:622
adcore_diff_mask
volatile uint16_t adcore_diff_mask
This variable is use to set the ADC core mask.
Definition: dev_buck_pconfig.c:32
BUCK_CONVERTER_s
BUCK control & monitoring data structure.
Definition: dev_buck_typedef.h:501
BUCK_SWITCH_NODE_SETTINGS_s::dead_time_falling
volatile uint16_t dead_time_falling
Dead time setting at falling edge of a half-bridge drive.
Definition: dev_buck_typedef.h:391
P33C_GPIO_INSTANCE_s::ODCx
union P33C_GPIO_INSTANCE_s::@4 ODCx
buckGPIO_Set
volatile uint16_t buckGPIO_Set(volatile struct BUCK_GPIO_INSTANCE_s *buckGPIOInstance)
This function sets the selected general purpose input/ouput pins.
Definition: dev_buck_pconfig.c:653
P33C_PGxIOCONL_OVREN_ASYNC_SWAP
#define P33C_PGxIOCONL_OVREN_ASYNC_SWAP
Definition: dev_buck_ptemp_pwm.h:455
BUCK_GPIO_INSTANCE_s
GPIO instance of the converter control GPIO.
Definition: dev_buck_typedef.h:470
P33C_PWM_GENERATOR_s::PGxIOCONL
union P33C_PWM_GENERATOR_s::@57 PGxIOCONL
BUCK_CONVERTER_SETTINGS_s::no_of_phases
volatile uint16_t no_of_phases
number of converter phases
Definition: dev_buck_typedef.h:325
BUCK_SWITCH_NODE_SETTINGS_s::period
volatile uint16_t period
Switching period.
Definition: dev_buck_typedef.h:385
BUCK_ADC_INPUT_SETTINGS_s::signed_result
volatile bool signed_result
input channel singed result mode enable bit
Definition: dev_buck_typedef.h:436
P33C_PWM_GENERATOR_s::PGxDC
union P33C_PWM_GENERATOR_s::@72 PGxDC
P33C_PGxIOCONL_OVREN_ASYNC
#define P33C_PGxIOCONL_OVREN_ASYNC
control bits in PGxIOCONL enabling/disabling the PWM output override in asynchronous mode
Definition: dev_buck_ptemp_pwm.h:454
buckPWM_ChannelInitialize
volatile uint16_t buckPWM_ChannelInitialize(volatile struct BUCK_CONVERTER_s *buckInstance)
This function initializes the output pins for the PWM output and the default buck PWM settings.
Definition: dev_buck_pconfig.c:110
BUCK_SWITCH_NODE_SETTINGS_s::high_resolution_enable
volatile bool high_resolution_enable
Selecting if PWM module should use high-resolution mode.
Definition: dev_buck_typedef.h:383
adcore_mask
volatile uint16_t adcore_mask
This variable is use to set the ADC core mask.
Definition: dev_buck_pconfig.c:25
P33C_PWM_MODULE_s::vMPER
union P33C_PWM_MODULE_s::@5 vMPER