Digital Power Starter Kit 3 Firmware
dsPIC33C Buck Converter Voltage Mode Control Example
dev_buck_ptemp_adc.h
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21 
22 /*
23  * File: dev_buck_ptemp_adc.h
24  * Author: M91406
25  * Comments: ADC Peripheral Special Function Register Configuration Template
26  * Revision history:
27  * 10/29/2020 1.0 initial release
28  */
29 
30 // This is a guard condition so that contents of this file are not included
31 // more than once.
32 #ifndef BUCK_CONVERTER_PERIPHERAL_CONFIGURATION_ADC_H
33 #define BUCK_CONVERTER_PERIPHERAL_CONFIGURATION_ADC_H
34 
35 #include <xc.h> // include processor files - each processor file is guarded.
36 #include <stdint.h> // include standard integer data types
37 #include <stdbool.h> // include standard boolean data types
38 #include <stddef.h> // include standard definition data types
39 
44 /* ********************************************************************************
45  * ADC BASE MODULE BASE REGISTERS CONFIGURATION
46  * *******************************************************************************/
51 #define ADC_POWERUP_TIMEOUT 5000
52 /* SLPxDAT: DACx SLOPE DATA REGISTER => Timing Register: User value will be set in code */
53 
54 // ADC specific declarations
59 #define ADC_CORE_MASK 0b0000000010001111
60 
65 #define ADC_CORE0_MASK_INDEX 0b0000000000000001
66 
71 #define ADC_CORE1_MASK_INDEX 0b0000000000000010
72 
77 #define ADC_CORE2_MASK_INDEX 0b0000000000000100
78 
83 #define ADC_CORE3_MASK_INDEX 0b0000000000001000
84 
89 #define ADC_SHRCORE_MASK_INDEX 0b0000000010000000
90 
91 /* ********************************************************************************
92  * ADC INPUT INSTANCE CONFIGURATION
93  * *******************************************************************************/
94 
95 
96 /* REGISTER VALUE DECLARATION TEMPLATE */
97 /* PCLKCON: PWM CLOCK CONTROL REGISTER
98 
99  ________________ BIT 15: HRRDY: High-Resolution Ready bit
100  | _______________ BIT 14: HRERR: High-Resolution Error bit
101  || ______________ BIT 13: (unimplemented)
102  ||| _____________ BIT 12: (unimplemented)
103  |||| ____________ BIT 11: (unimplemented)
104  ||||| ___________ BIT 10: (unimplemented)
105  |||||| __________ BIT 9: (unimplemented)
106  ||||||| _________ BIT 8: LOCK: Lock bit
107  |||||||| ________ BIT 7: (unimplemented)
108  ||||||||| _______ BIT 6: (unimplemented)
109  |||||||||| ______ BIT 5: DIVSEL[1:0]: PWM Clock Divider Selection bits
110  ||||||||||| _____ BIT 4:
111  |||||||||||| ____ BIT 3: (unimplemented)
112  ||||||||||||| ___ BIT 2: (unimplemented)
113  |||||||||||||| __ BIT 1: MCLKSEL[1:0]: PWM Master Clock Selection bits
114  ||||||||||||||| _ BIT 0:
115  |||||||||||||||| *//*
116 #define REG_PCLKCON 0b0000000000000011 */
117 
118 
119 
120 #endif /* BUCK_CONVERTER_PERIPHERAL_CONFIGURATION_ADC_H */
121