Digital Power Starter Kit 3 Firmware
dsPIC33C Buck Converter Voltage Mode Control Example
dev_buck_ptemp_pwm.h
1 
33 /*
34  * File: dev_buck_ptemp_pwm.h
35  * Author: M91406
36  * Comments: PWM Peripheral Special Function Register Configuration Template
37  * Revision history:
38  * 10/29/2020 1.0 initial release
39  */
40 
41 // This is a guard condition so that contents of this file are not included
42 // more than once.
43 #ifndef BUCK_CONVERTER_PERIPHERAL_CONFIGURATION_PWM_H
44 #define BUCK_CONVERTER_PERIPHERAL_CONFIGURATION_PWM_H
45 
46 #include <xc.h> // include processor files - each processor file is guarded.
47 #include <stdint.h> // include standard integer data types
48 #include <stdbool.h> // include standard boolean data types
49 #include <stddef.h> // include standard definition data types
50 
55 /* ********************************************************************************
56  * PWM MODULE BASE REGISTER CONFIGURATION
57  * *******************************************************************************/
62 /*
63  ________________ BIT 15: HRRDY: High-Resolution Ready bit
64  | _______________ BIT 14: HRERR: High-Resolution Error bit
65  || ______________ BIT 13: (unimplemented)
66  ||| _____________ BIT 12: (unimplemented)
67  |||| ____________ BIT 11: (unimplemented)
68  ||||| ___________ BIT 10: (unimplemented)
69  |||||| __________ BIT 9: (unimplemented)
70  ||||||| _________ BIT 8: LOCK: Lock bit
71  |||||||| ________ BIT 7: (unimplemented)
72  ||||||||| _______ BIT 6: (unimplemented)
73  |||||||||| ______ BIT 5: DIVSEL[1:0]: PWM Clock Divider Selection bits
74  ||||||||||| _____ BIT 4:
75  |||||||||||| ____ BIT 3: (unimplemented)
76  ||||||||||||| ___ BIT 2: (unimplemented)
77  |||||||||||||| __ BIT 1: MCLKSEL[1:0]: PWM Master Clock Selection bits
78  ||||||||||||||| _ BIT 0:
79  |||||||||||||||| */
80 #define REG_PCLKCON 0b0000000000000011
81 
86 /*
87 
88  ________________ BIT 15: (unimplemented)
89  | _______________ BIT 14: (unimplemented)
90  || ______________ BIT 13: (unimplemented)
91  ||| _____________ BIT 12: (unimplemented)
92  |||| ____________ BIT 11: (unimplemented)
93  ||||| ___________ BIT 10: (unimplemented)
94  |||||| __________ BIT 9: (unimplemented)
95  ||||||| _________ BIT 8: (unimplemented)
96  |||||||| ________ BIT 7: CTA8EN: Enable Trigger Output from PWM Generator #8 as Source for Combinational Trigger A bit
97  ||||||||| _______ BIT 6: CTA7EN: Enable Trigger Output from PWM Generator #7 as Source for Combinational Trigger A bit
98  |||||||||| ______ BIT 5: CTA6EN: Enable Trigger Output from PWM Generator #6 as Source for Combinational Trigger A bit
99  ||||||||||| _____ BIT 4: CTA5EN: Enable Trigger Output from PWM Generator #5 as Source for Combinational Trigger A bit
100  |||||||||||| ____ BIT 3: CTA4EN: Enable Trigger Output from PWM Generator #4 as Source for Combinational Trigger A bit
101  ||||||||||||| ___ BIT 2: CTA3EN: Enable Trigger Output from PWM Generator #3 as Source for Combinational Trigger A bit
102  |||||||||||||| __ BIT 1: CTA2EN: Enable Trigger Output from PWM Generator #2 as Source for Combinational Trigger A bit
103  ||||||||||||||| _ BIT 0: CTA1EN: Enable Trigger Output from PWM Generator #1 as Source for Combinational Trigger A bit
104  |||||||||||||||| */
105 #define REG_CMBTRIGL 0b0000000000000000
106 
111 /* CMBTRIGH: COMBINATIONAL TRIGGER REGISTER HIGH
112 
113  ________________ BIT 15: (unimplemented)
114  | _______________ BIT 14: (unimplemented)
115  || ______________ BIT 13: (unimplemented)
116  ||| _____________ BIT 12: (unimplemented)
117  |||| ____________ BIT 11: (unimplemented)
118  ||||| ___________ BIT 10: (unimplemented)
119  |||||| __________ BIT 9: (unimplemented)
120  ||||||| _________ BIT 8: (unimplemented)
121  |||||||| ________ BIT 7: CTB8EN: Enable Trigger Output from PWM Generator #8 as Source for Combinational Trigger B bit
122  ||||||||| _______ BIT 6: CTB7EN: Enable Trigger Output from PWM Generator #7 as Source for Combinational Trigger B bit
123  |||||||||| ______ BIT 5: CTB6EN: Enable Trigger Output from PWM Generator #6 as Source for Combinational Trigger B bit
124  ||||||||||| _____ BIT 4: CTB5EN: Enable Trigger Output from PWM Generator #5 as Source for Combinational Trigger B bit
125  |||||||||||| ____ BIT 3: CTB4EN: Enable Trigger Output from PWM Generator #4 as Source for Combinational Trigger B bit
126  ||||||||||||| ___ BIT 2: CTB3EN: Enable Trigger Output from PWM Generator #3 as Source for Combinational Trigger B bit
127  |||||||||||||| __ BIT 1: CTB2EN: Enable Trigger Output from PWM Generator #2 as Source for Combinational Trigger B bit
128  ||||||||||||||| _ BIT 0: CTB1EN: Enable Trigger Output from PWM Generator #1 as Source for Combinational Trigger B bit
129  |||||||||||||||| */
130 #define REG_CMBTRIGH 0b0000000000000000
131 
136 /*
137 
138  ________________ BIT 15: PWMS1y[3:0]: Combinatorial PWM Logic Source #1 Selection bits
139  | _______________ BIT 14:
140  || ______________ BIT 13:
141  ||| _____________ BIT 12:
142  |||| ____________ BIT 11: PWMS2y[3:0]: Combinatorial PWM Logic Source #1 Selection bits
143  ||||| ___________ BIT 10:
144  |||||| __________ BIT 9:
145  ||||||| _________ BIT 8:
146  |||||||| ________ BIT 7: S1yPOL: Combinatorial PWM Logic Source #1 Polarity bit
147  ||||||||| _______ BIT 6: S2yPOL: Combinatorial PWM Logic Source #2 Polarity bit
148  |||||||||| ______ BIT 5: PWMLFy[1:0]: Combinatorial PWM Logic Function Selection bits
149  ||||||||||| _____ BIT 4:
150  |||||||||||| ____ BIT 3: (unimplemented)
151  ||||||||||||| ___ BIT 2: PWMLFyD[2:0]: Combinatorial PWM Logic Destination Selection bits
152  |||||||||||||| __ BIT 1:
153  ||||||||||||||| _ BIT 0:
154  |||||||||||||||| */
155 #define REG_LOGCONA 0b0000000000000000
156 
161 /* LOGCONB: COMBINATORIAL PWM LOGIC CONTROL REGISTER B
162 
163  ________________ BIT 15: PWMS1y[3:0]: Combinatorial PWM Logic Source #1 Selection bits
164  | _______________ BIT 14:
165  || ______________ BIT 13:
166  ||| _____________ BIT 12:
167  |||| ____________ BIT 11: PWMS2y[3:0]: Combinatorial PWM Logic Source #1 Selection bits
168  ||||| ___________ BIT 10:
169  |||||| __________ BIT 9:
170  ||||||| _________ BIT 8:
171  |||||||| ________ BIT 7: S1yPOL: Combinatorial PWM Logic Source #1 Polarity bit
172  ||||||||| _______ BIT 6: S2yPOL: Combinatorial PWM Logic Source #2 Polarity bit
173  |||||||||| ______ BIT 5: PWMLFy[1:0]: Combinatorial PWM Logic Function Selection bits
174  ||||||||||| _____ BIT 4:
175  |||||||||||| ____ BIT 3: (unimplemented)
176  ||||||||||||| ___ BIT 2: PWMLFyD[2:0]: Combinatorial PWM Logic Destination Selection bits
177  |||||||||||||| __ BIT 1:
178  ||||||||||||||| _ BIT 0:
179  |||||||||||||||| */
180 #define REG_LOGCONB 0b0000000000000000
181 
186 /*
187 
188  ________________ BIT 15: PWMS1y[3:0]: Combinatorial PWM Logic Source #1 Selection bits
189  | _______________ BIT 14:
190  || ______________ BIT 13:
191  ||| _____________ BIT 12:
192  |||| ____________ BIT 11: PWMS2y[3:0]: Combinatorial PWM Logic Source #1 Selection bits
193  ||||| ___________ BIT 10:
194  |||||| __________ BIT 9:
195  ||||||| _________ BIT 8:
196  |||||||| ________ BIT 7: S1yPOL: Combinatorial PWM Logic Source #1 Polarity bit
197  ||||||||| _______ BIT 6: S2yPOL: Combinatorial PWM Logic Source #2 Polarity bit
198  |||||||||| ______ BIT 5: PWMLFy[1:0]: Combinatorial PWM Logic Function Selection bits
199  ||||||||||| _____ BIT 4:
200  |||||||||||| ____ BIT 3: (unimplemented)
201  ||||||||||||| ___ BIT 2: PWMLFyD[2:0]: Combinatorial PWM Logic Destination Selection bits
202  |||||||||||||| __ BIT 1:
203  ||||||||||||||| _ BIT 0:
204  |||||||||||||||| */
205 #define REG_LOGCONC 0b0000000000000000
206 
211 /*
212 
213  ________________ BIT 15: PWMS1y[3:0]: Combinatorial PWM Logic Source #1 Selection bits
214  | _______________ BIT 14:
215  || ______________ BIT 13:
216  ||| _____________ BIT 12:
217  |||| ____________ BIT 11: PWMS2y[3:0]: Combinatorial PWM Logic Source #1 Selection bits
218  ||||| ___________ BIT 10:
219  |||||| __________ BIT 9:
220  ||||||| _________ BIT 8:
221  |||||||| ________ BIT 7: S1yPOL: Combinatorial PWM Logic Source #1 Polarity bit
222  ||||||||| _______ BIT 6: S2yPOL: Combinatorial PWM Logic Source #2 Polarity bit
223  |||||||||| ______ BIT 5: PWMLFy[1:0]: Combinatorial PWM Logic Function Selection bits
224  ||||||||||| _____ BIT 4:
225  |||||||||||| ____ BIT 3: (unimplemented)
226  ||||||||||||| ___ BIT 2: PWMLFyD[2:0]: Combinatorial PWM Logic Destination Selection bits
227  |||||||||||||| __ BIT 1:
228  ||||||||||||||| _ BIT 0:
229  |||||||||||||||| */
230 #define REG_LOGCOND 0b0000000000000000
231 
236 /*
237 
238  ________________ BIT 15: PWMS1y[3:0]: Combinatorial PWM Logic Source #1 Selection bits
239  | _______________ BIT 14:
240  || ______________ BIT 13:
241  ||| _____________ BIT 12:
242  |||| ____________ BIT 11: PWMS2y[3:0]: Combinatorial PWM Logic Source #1 Selection bits
243  ||||| ___________ BIT 10:
244  |||||| __________ BIT 9:
245  ||||||| _________ BIT 8:
246  |||||||| ________ BIT 7: S1yPOL: Combinatorial PWM Logic Source #1 Polarity bit
247  ||||||||| _______ BIT 6: S2yPOL: Combinatorial PWM Logic Source #2 Polarity bit
248  |||||||||| ______ BIT 5: PWMLFy[1:0]: Combinatorial PWM Logic Function Selection bits
249  ||||||||||| _____ BIT 4:
250  |||||||||||| ____ BIT 3: (unimplemented)
251  ||||||||||||| ___ BIT 2: PWMLFyD[2:0]: Combinatorial PWM Logic Destination Selection bits
252  |||||||||||||| __ BIT 1:
253  ||||||||||||||| _ BIT 0:
254  |||||||||||||||| */
255 #define REG_LOGCONE 0b0000000000000000
256 
261 /*
262 
263  ________________ BIT 15: PWMS1y[3:0]: Combinatorial PWM Logic Source #1 Selection bits
264  | _______________ BIT 14:
265  || ______________ BIT 13:
266  ||| _____________ BIT 12:
267  |||| ____________ BIT 11: PWMS2y[3:0]: Combinatorial PWM Logic Source #1 Selection bits
268  ||||| ___________ BIT 10:
269  |||||| __________ BIT 9:
270  ||||||| _________ BIT 8:
271  |||||||| ________ BIT 7: S1yPOL: Combinatorial PWM Logic Source #1 Polarity bit
272  ||||||||| _______ BIT 6: S2yPOL: Combinatorial PWM Logic Source #2 Polarity bit
273  |||||||||| ______ BIT 5: PWMLFy[1:0]: Combinatorial PWM Logic Function Selection bits
274  ||||||||||| _____ BIT 4:
275  |||||||||||| ____ BIT 3: (unimplemented)
276  ||||||||||||| ___ BIT 2: PWMLFyD[2:0]: Combinatorial PWM Logic Destination Selection bits
277  |||||||||||||| __ BIT 1:
278  ||||||||||||||| _ BIT 0:
279  |||||||||||||||| */
280 #define REG_LOGCONF 0b0000000000000000
281 
286 /*
287 
288  ________________ BIT 15: EVTyOEN: PWM Event Output Enable bit
289  | _______________ BIT 14: EVTyPOL: PWM Event Output Polarity bit
290  || ______________ BIT 13: EVTySTRD: PWM Event Output Stretch Disable bit
291  ||| _____________ BIT 12: EVTySYNC: PWM Event Output Sync bit
292  |||| ____________ BIT 11: (unimplemented)
293  ||||| ___________ BIT 10: (unimplemented)
294  |||||| __________ BIT 9: (unimplemented)
295  ||||||| _________ BIT 8: (unimplemented)
296  |||||||| ________ BIT 7: EVTySEL[3:0]: PWM Event Selection bits
297  ||||||||| _______ BIT 6:
298  |||||||||| ______ BIT 5:
299  ||||||||||| _____ BIT 4:
300  |||||||||||| ____ BIT 3: (unimplemented)
301  ||||||||||||| ___ BIT 2: EVTyPGS[2:0]: PWM Event Source Selection bits
302  |||||||||||||| __ BIT 1:
303  ||||||||||||||| _ BIT 0:
304  |||||||||||||||| */
305 #define REG_PWMEVTA 0b0000000000000000
306 
311 /*
312 
313  ________________ BIT 15: EVTyOEN: PWM Event Output Enable bit
314  | _______________ BIT 14: EVTyPOL: PWM Event Output Polarity bit
315  || ______________ BIT 13: EVTySTRD: PWM Event Output Stretch Disable bit
316  ||| _____________ BIT 12: EVTySYNC: PWM Event Output Sync bit
317  |||| ____________ BIT 11: (unimplemented)
318  ||||| ___________ BIT 10: (unimplemented)
319  |||||| __________ BIT 9: (unimplemented)
320  ||||||| _________ BIT 8: (unimplemented)
321  |||||||| ________ BIT 7: EVTySEL[3:0]: PWM Event Selection bits
322  ||||||||| _______ BIT 6:
323  |||||||||| ______ BIT 5:
324  ||||||||||| _____ BIT 4:
325  |||||||||||| ____ BIT 3: (unimplemented)
326  ||||||||||||| ___ BIT 2: EVTyPGS[2:0]: PWM Event Source Selection bits
327  |||||||||||||| __ BIT 1:
328  ||||||||||||||| _ BIT 0:
329  |||||||||||||||| */
330 #define REG_PWMEVTB 0b0000000000000000
331 
336 /*
337 
338  ________________ BIT 15: EVTyOEN: PWM Event Output Enable bit
339  | _______________ BIT 14: EVTyPOL: PWM Event Output Polarity bit
340  || ______________ BIT 13: EVTySTRD: PWM Event Output Stretch Disable bit
341  ||| _____________ BIT 12: EVTySYNC: PWM Event Output Sync bit
342  |||| ____________ BIT 11: (unimplemented)
343  ||||| ___________ BIT 10: (unimplemented)
344  |||||| __________ BIT 9: (unimplemented)
345  ||||||| _________ BIT 8: (unimplemented)
346  |||||||| ________ BIT 7: EVTySEL[3:0]: PWM Event Selection bits
347  ||||||||| _______ BIT 6:
348  |||||||||| ______ BIT 5:
349  ||||||||||| _____ BIT 4:
350  |||||||||||| ____ BIT 3: (unimplemented)
351  ||||||||||||| ___ BIT 2: EVTyPGS[2:0]: PWM Event Source Selection bits
352  |||||||||||||| __ BIT 1:
353  ||||||||||||||| _ BIT 0:
354  |||||||||||||||| */
355 #define REG_PWMEVTC 0b0000000000000000
356 
361 /*
362 
363  ________________ BIT 15: EVTyOEN: PWM Event Output Enable bit
364  | _______________ BIT 14: EVTyPOL: PWM Event Output Polarity bit
365  || ______________ BIT 13: EVTySTRD: PWM Event Output Stretch Disable bit
366  ||| _____________ BIT 12: EVTySYNC: PWM Event Output Sync bit
367  |||| ____________ BIT 11: (unimplemented)
368  ||||| ___________ BIT 10: (unimplemented)
369  |||||| __________ BIT 9: (unimplemented)
370  ||||||| _________ BIT 8: (unimplemented)
371  |||||||| ________ BIT 7: EVTySEL[3:0]: PWM Event Selection bits
372  ||||||||| _______ BIT 6:
373  |||||||||| ______ BIT 5:
374  ||||||||||| _____ BIT 4:
375  |||||||||||| ____ BIT 3: (unimplemented)
376  ||||||||||||| ___ BIT 2: EVTyPGS[2:0]: PWM Event Source Selection bits
377  |||||||||||||| __ BIT 1:
378  ||||||||||||||| _ BIT 0:
379  |||||||||||||||| */
380 #define REG_PWMEVTD 0b0000000000000000
381 
386 /*
387 
388  ________________ BIT 15: EVTyOEN: PWM Event Output Enable bit
389  | _______________ BIT 14: EVTyPOL: PWM Event Output Polarity bit
390  || ______________ BIT 13: EVTySTRD: PWM Event Output Stretch Disable bit
391  ||| _____________ BIT 12: EVTySYNC: PWM Event Output Sync bit
392  |||| ____________ BIT 11: (unimplemented)
393  ||||| ___________ BIT 10: (unimplemented)
394  |||||| __________ BIT 9: (unimplemented)
395  ||||||| _________ BIT 8: (unimplemented)
396  |||||||| ________ BIT 7: EVTySEL[3:0]: PWM Event Selection bits
397  ||||||||| _______ BIT 6:
398  |||||||||| ______ BIT 5:
399  ||||||||||| _____ BIT 4:
400  |||||||||||| ____ BIT 3: (unimplemented)
401  ||||||||||||| ___ BIT 2: EVTyPGS[2:0]: PWM Event Source Selection bits
402  |||||||||||||| __ BIT 1:
403  ||||||||||||||| _ BIT 0:
404  |||||||||||||||| */
405 #define REG_PWMEVTE 0b0000000000000000
406 
411 /*
412 
413  ________________ BIT 15: EVTyOEN: PWM Event Output Enable bit
414  | _______________ BIT 14: EVTyPOL: PWM Event Output Polarity bit
415  || ______________ BIT 13: EVTySTRD: PWM Event Output Stretch Disable bit
416  ||| _____________ BIT 12: EVTySYNC: PWM Event Output Sync bit
417  |||| ____________ BIT 11: (unimplemented)
418  ||||| ___________ BIT 10: (unimplemented)
419  |||||| __________ BIT 9: (unimplemented)
420  ||||||| _________ BIT 8: (unimplemented)
421  |||||||| ________ BIT 7: EVTySEL[3:0]: PWM Event Selection bits
422  ||||||||| _______ BIT 6:
423  |||||||||| ______ BIT 5:
424  ||||||||||| _____ BIT 4:
425  |||||||||||| ____ BIT 3: (unimplemented)
426  ||||||||||||| ___ BIT 2: EVTyPGS[2:0]: PWM Event Source Selection bits
427  |||||||||||||| __ BIT 1:
428  ||||||||||||||| _ BIT 0:
429  |||||||||||||||| */
430 #define REG_PWMEVTF 0b0000000000000000
431 
432 /* ********************************************************************************
433  * PWM GENERATOR CONFIGURATION
434  * *******************************************************************************/
439 #define P33C_PGxCONL_PWM_ON 0x8000
440 
444 #define P33C_PGxCONL_HRES_EN 0x0080
445 
449 #define P33C_PGxIOCONL_OVREN_SYNC 0x3000
450 
454 #define P33C_PGxIOCONL_OVREN_ASYNC 0x2000
455 #define P33C_PGxIOCONL_OVREN_ASYNC_SWAP 0x1000
456 
460 #define P33C_PGxIOCONH_PEN_SYNC 0x000C
461 
465 #define P33C_PGxIOCONH_PEN_ASYNC 0x0008
466 #define P33C_PGxIOCONH_PEN_ASYNC_SWAP 0x0004
467 
471 #define P33C_PGxSTAT_UPDREQ 0x0008
472 
476 #define P33C_PGxCONH_MPERSEL 0x4000
477 
481 #define P33C_PGxCONH_UPDMOD_MSTR 0b001
482 
486 #define P33C_PGxCONH_UPDMOD_SLV 0b011
487 
488 // ==============================================================================================
489 // BUCK converter Peripheral Configuration for Voltage and Average Current Mode Control
490 // ==============================================================================================
495 /*
496 
497  ________________ BIT 15: ON: Enable: PWM Generator Enable
498  | _______________ BIT 14: (reserved)
499  || ______________ BIT 13: (unimplemented)
500  ||| _____________ BIT 12: (unimplemented)
501  |||| ____________ BIT 11: (unimplemented)
502  ||||| ___________ BIT 10: TRGCNT[2:0]: Trigger Count Selection
503  |||||| __________ BIT 9:
504  ||||||| _________ BIT 8:
505  |||||||| ________ BIT 7: HREN: PWM Generator x High-Resolution Enable
506  ||||||||| _______ BIT 6: (unimplemented)
507  |||||||||| ______ BIT 5: (unimplemented)
508  ||||||||||| _____ BIT 4: CLKSEL[1:0]: Clock Selection
509  |||||||||||| ____ BIT 3:
510  ||||||||||||| ___ BIT 2: MODSEL[2:0]: Mode Selection
511  |||||||||||||| __ BIT 1:
512  ||||||||||||||| _ BIT 0:
513  |||||||||||||||| */
514 #define REG_PGxCONL 0b0000000010001000
515 
520 /*
521 
522  ________________ BIT 15: MDCSEL: Master Duty Cycle Register Selection: 0 = PWM Generator uses PGxDC register
523  | _______________ BIT 14: MPERSEL: Master Period Register Selection: 1 = PWM Generator uses MPER register
524  || ______________ BIT 13: MPHSEL: Master Phase Register Selection: 0 = PWM Generator uses PGxPHASE register
525  ||| _____________ BIT 12: (unimplemented)
526  |||| ____________ BIT 11: MSTEN: Master Update Enable: 0 = PWM Generator does not broadcast the UPDREQ status bit state or EOC signal
527  ||||| ___________ BIT 10: UPDMOD[2:0]: PWM Buffer Update Mode Selection: 001 = Immediate update
528  |||||| __________ BIT 9:
529  ||||||| _________ BIT 8:
530  |||||||| ________ BIT 7: (reserved)
531  ||||||||| _______ BIT 6: TRGMOD: PWM Generator Trigger Mode Selection: PWM Generator operates in Retriggerable mode
532  |||||||||| ______ BIT 5: (unimplemented)
533  ||||||||||| _____ BIT 4: (unimplemented)
534  |||||||||||| ____ BIT 3: SOCS[3:0]: Start-of-Cycle Selection: Local EOC ? PWM Generator is self-triggered
535  ||||||||||||| ___ BIT 2:
536  |||||||||||||| __ BIT 1:
537  ||||||||||||||| _ BIT 0:
538  |||||||||||||||| */
539 #define REG_PGxCONH 0b0000000100000000
540 
545 /* PGxIOCONL: PWM GENERATOR x I/O CONTROL REGISTER LOW
546 
547  ________________ BIT 15: CLMOD: Current-Limit Mode Selection
548  | _______________ BIT 14: SWAP: Swap PWM Signals to PWMxH and PWMxL Device Pins
549  || ______________ BIT 13: OVRENH: User Override Enable for PWMxH Pin
550  ||| _____________ BIT 12: OVRENL: User Override Enable for PWMxL Pin
551  |||| ____________ BIT 11: OVRDAT[1:0]: Data for PWMxH/PWMxL Pins if Override is Enabled
552  ||||| ___________ BIT 10:
553  |||||| __________ BIT 9: OSYNC[1:0]: User Output Override Synchronization Control
554  ||||||| _________ BIT 8:
555  |||||||| ________ BIT 7: FLTDAT[1:0]: Data for PWMxH/PWMxL Pins if Fault Event is Active
556  ||||||||| _______ BIT 6:
557  |||||||||| ______ BIT 5: CLDAT[1:0]: Data for PWMxH/PWMxL Pins if Current-Limit Event is Active
558  ||||||||||| _____ BIT 4:
559  |||||||||||| ____ BIT 3: FFDAT[1:0]: Data for PWMxH/PWMxL Pins if Feed-Forward Event is Active
560  ||||||||||||| ___ BIT 2:
561  |||||||||||||| __ BIT 1: DBDAT[1:0]: Data for PWMxH/PWMxL Pins if Debug Mode is Active
562  ||||||||||||||| _ BIT 0:
563  |||||||||||||||| */
564 #define REG_PGxIOCONL 0b0011000000000000
565 
570 /*
571 
572  ________________ BIT 15: (unimplemented)
573  | _______________ BIT 14: CAPSRC[2:0]: Time Base Capture Source Selection
574  || ______________ BIT 13:
575  ||| _____________ BIT 12:
576  |||| ____________ BIT 11: (unimplemented)
577  ||||| ___________ BIT 10: (unimplemented)
578  |||||| __________ BIT 9: (unimplemented)
579  ||||||| _________ BIT 8: DTCMPSEL: Dead-Time Compensation Select
580  |||||||| ________ BIT 7: (unimplemented)
581  ||||||||| _______ BIT 6: (unimplemented)
582  |||||||||| ______ BIT 5: PMOD[1:0]: PWM Generator Output Mode Selection
583  ||||||||||| _____ BIT 4:
584  |||||||||||| ____ BIT 3: PENH: PWMxH Output Port Enable
585  ||||||||||||| ___ BIT 2: PENL: PWMxL Output Port Enable
586  |||||||||||||| __ BIT 1: POLH: PWMxH Output Polarity
587  ||||||||||||||| _ BIT 0: POLL: PWMxL Output Polarity
588  |||||||||||||||| */
589 #define REG_PGxIOCONH 0b0000000000000000
590 
595 /*
596 
597  ________________ BIT 15: ADTR1PS[4:0]: ADC Trigger 1 Postscaler Selection
598  | _______________ BIT 14:
599  || ______________ BIT 13:
600  ||| _____________ BIT 12:
601  |||| ____________ BIT 11:
602  ||||| ___________ BIT 10: ADTR1EN3: ADC Trigger 1 Source is PGxTRIGC Compare Event Enable
603  |||||| __________ BIT 9: ADTR1EN2: ADC Trigger 1 Source is PGxTRIGB Compare Event Enable
604  ||||||| _________ BIT 8: ADTR1EN1: ADC Trigger 1 Source is PGxTRIGA Compare Event Enable
605  |||||||| ________ BIT 7: (unimplemented)
606  ||||||||| _______ BIT 6: (unimplemented)
607  |||||||||| ______ BIT 5: (unimplemented)
608  ||||||||||| _____ BIT 4: UPDTRG[1:0]: Update Trigger Selection
609  |||||||||||| ____ BIT 3:
610  ||||||||||||| ___ BIT 2: PGTRGSEL[2:0]: PWM Generator Trigger Output Selection
611  |||||||||||||| __ BIT 1:
612  ||||||||||||||| _ BIT 0:
613  |||||||||||||||| */
614 #define REG_PGxEVTL 0b0000000100011001
615 
620 /*
621 
622  ________________ BIT 15: FLTIEN: PCI Fault Interrupt Enable
623  | _______________ BIT 14: CLIEN: PCI Current-Limit Interrupt Enable
624  || ______________ BIT 13: FFIEN: PCI Feed-Forward Interrupt Enable
625  ||| _____________ BIT 12: SIEN: PCI Sync Interrupt Enable
626  |||| ____________ BIT 11: (unimplemented)
627  ||||| ___________ BIT 10: (unimplemented)
628  |||||| __________ BIT 9: IEVTSEL[1:0]: Interrupt Event Selection = Interrupts CPU at TRIGA compare event
629  ||||||| _________ BIT 8:
630  |||||||| ________ BIT 7: ADTR2EN3: ADC Trigger 2 Source is PGxTRIGC Compare Event Enable
631  ||||||||| _______ BIT 6: ADTR2EN2: ADC Trigger 2 Source is PGxTRIGB Compare Event Enable
632  |||||||||| ______ BIT 5: ADTR2EN1: ADC Trigger 2 Source is PGxTRIGA Compare Event Enable
633  ||||||||||| _____ BIT 4: ADTR1OFS[4:0]: ADC Trigger 1 Offset Selection
634  |||||||||||| ____ BIT 3:
635  ||||||||||||| ___ BIT 2:
636  |||||||||||||| __ BIT 1:
637  ||||||||||||||| _ BIT 0:
638  |||||||||||||||| */
639 #define REG_PGxEVTH 0b0000000101000000
640 
645 /*
646 
647  ________________ BIT 15: TSYNCDIS: Termination Synchronization Disable
648  | _______________ BIT 14: TERM[2:0]: Termination Event Selection
649  || ______________ BIT 13:
650  ||| _____________ BIT 12:
651  |||| ____________ BIT 11: AQPS: Acceptance Qualifier Polarity Selection
652  ||||| ___________ BIT 10: AQSS[2:0]: Acceptance Qualifier Source Selection
653  |||||| __________ BIT 9:
654  ||||||| _________ BIT 8:
655  |||||||| ________ BIT 7: SWTERM: PCI Software Termination
656  ||||||||| _______ BIT 6: PSYNC: PCI Synchronization Control
657  |||||||||| ______ BIT 5: PPS: PCI Polarity Selection
658  ||||||||||| _____ BIT 4: PSS[4:0]: PCI Source Selection
659  |||||||||||| ____ BIT 3:
660  ||||||||||||| ___ BIT 2:
661  |||||||||||||| __ BIT 1:
662  ||||||||||||||| _ BIT 0:
663  |||||||||||||||| */
664 //#define REG_PGxCLPCIL 0b0001101000011011 // Peak Current Mode Configuration
665 #define REG_PGxCLPCIL 0b0000000000000000
666 
671 /*
672 
673  ________________ BIT 15: BPEN: PCI Bypass Enable
674  | _______________ BIT 14: BPSEL[2:0]: PCI Bypass Source Selection
675  || ______________ BIT 13:
676  ||| _____________ BIT 12:
677  |||| ____________ BIT 11: (unimplemented)
678  ||||| ___________ BIT 10: ACP[2:0]: PCI Acceptance Criteria Selection
679  |||||| __________ BIT 9:
680  ||||||| _________ BIT 8:
681  |||||||| ________ BIT 7: SWPCI: Software PCI Control
682  ||||||||| _______ BIT 6: SWPCIM[1:0]: Software PCI Control Mode
683  |||||||||| ______ BIT 5:
684  ||||||||||| _____ BIT 4: LATMOD: PCI SR Latch Mode
685  |||||||||||| ____ BIT 3: TQPS: Termination Qualifier Polarity Selection
686  ||||||||||||| ___ BIT 2: TQSS[2:0]: Termination Qualifier Source Selection
687  |||||||||||||| __ BIT 1:
688  ||||||||||||||| _ BIT 0:
689  |||||||||||||||| */
690 //#define REG_PGxCLPCIH 0b0000011000000000 // Peak Current Mode Configuration
691 #define REG_PGxCLPCIH 0b0000000000000000
692 
697 /*
698 
699  ________________ BIT 15: TSYNCDIS: Termination Synchronization Disable
700  | _______________ BIT 14: TERM[2:0]: Termination Event Selection
701  || ______________ BIT 13:
702  ||| _____________ BIT 12:
703  |||| ____________ BIT 11: AQPS: Acceptance Qualifier Polarity Selection
704  ||||| ___________ BIT 10: AQSS[2:0]: Acceptance Qualifier Source Selection
705  |||||| __________ BIT 9:
706  ||||||| _________ BIT 8:
707  |||||||| ________ BIT 7: SWTERM: PCI Software Termination
708  ||||||||| _______ BIT 6: PSYNC: PCI Synchronization Control
709  |||||||||| ______ BIT 5: PPS: PCI Polarity Selection
710  ||||||||||| _____ BIT 4: PSS[4:0]: PCI Source Selection
711  |||||||||||| ____ BIT 3:
712  ||||||||||||| ___ BIT 2:
713  |||||||||||||| __ BIT 1:
714  ||||||||||||||| _ BIT 0:
715  |||||||||||||||| */
716 #define REG_PGxFPCIL 0b0000000000000000
717 
722 /*
723 
724  ________________ BIT 15: BPEN: PCI Bypass Enable
725  | _______________ BIT 14: BPSEL[2:0]: PCI Bypass Source Selection
726  || ______________ BIT 13:
727  ||| _____________ BIT 12:
728  |||| ____________ BIT 11: (unimplemented)
729  ||||| ___________ BIT 10: ACP[2:0]: PCI Acceptance Criteria Selection
730  |||||| __________ BIT 9:
731  ||||||| _________ BIT 8:
732  |||||||| ________ BIT 7: SWPCI: Software PCI Control
733  ||||||||| _______ BIT 6: SWPCIM[1:0]: Software PCI Control Mode
734  |||||||||| ______ BIT 5:
735  ||||||||||| _____ BIT 4: LATMOD: PCI SR Latch Mode
736  |||||||||||| ____ BIT 3: TQPS: Termination Qualifier Polarity Selection
737  ||||||||||||| ___ BIT 2: TQSS[2:0]: Termination Qualifier Source Selection
738  |||||||||||||| __ BIT 1:
739  ||||||||||||||| _ BIT 0:
740  |||||||||||||||| */
741 #define REG_PGxFPCIH 0b0000000000000000
742 
747 /* PGxFFPCIL: PWM GENERATOR FEED FORWARD PCI REGISTER LOW
748 
749  ________________ BIT 15: TSYNCDIS: Termination Synchronization Disable
750  | _______________ BIT 14: TERM[2:0]: Termination Event Selection
751  || ______________ BIT 13:
752  ||| _____________ BIT 12:
753  |||| ____________ BIT 11: AQPS: Acceptance Qualifier Polarity Selection
754  ||||| ___________ BIT 10: AQSS[2:0]: Acceptance Qualifier Source Selection
755  |||||| __________ BIT 9:
756  ||||||| _________ BIT 8:
757  |||||||| ________ BIT 7: SWTERM: PCI Software Termination
758  ||||||||| _______ BIT 6: PSYNC: PCI Synchronization Control
759  |||||||||| ______ BIT 5: PPS: PCI Polarity Selection
760  ||||||||||| _____ BIT 4: PSS[4:0]: PCI Source Selection
761  |||||||||||| ____ BIT 3:
762  ||||||||||||| ___ BIT 2:
763  |||||||||||||| __ BIT 1:
764  ||||||||||||||| _ BIT 0:
765  |||||||||||||||| */
766 #define REG_PGxFFPCIL 0b0000000000000000
767 
772 /*
773 
774  ________________ BIT 15: BPEN: PCI Bypass Enable
775  | _______________ BIT 14: BPSEL[2:0]: PCI Bypass Source Selection
776  || ______________ BIT 13:
777  ||| _____________ BIT 12:
778  |||| ____________ BIT 11: (unimplemented)
779  ||||| ___________ BIT 10: ACP[2:0]: PCI Acceptance Criteria Selection
780  |||||| __________ BIT 9:
781  ||||||| _________ BIT 8:
782  |||||||| ________ BIT 7: SWPCI: Software PCI Control
783  ||||||||| _______ BIT 6: SWPCIM[1:0]: Software PCI Control Mode
784  |||||||||| ______ BIT 5:
785  ||||||||||| _____ BIT 4: LATMOD: PCI SR Latch Mode
786  |||||||||||| ____ BIT 3: TQPS: Termination Qualifier Polarity Selection
787  ||||||||||||| ___ BIT 2: TQSS[2:0]: Termination Qualifier Source Selection
788  |||||||||||||| __ BIT 1:
789  ||||||||||||||| _ BIT 0:
790  |||||||||||||||| */
791 #define REG_PGxFFPCIH 0b0000000000000000
792 
797 /* PGxSPCIL: PWM GENERATOR SOFTWARE PCI REGISTER LOW
798 
799  ________________ BIT 15: TSYNCDIS: Termination Synchronization Disable
800  | _______________ BIT 14: TERM[2:0]: Termination Event Selection
801  || ______________ BIT 13:
802  ||| _____________ BIT 12:
803  |||| ____________ BIT 11: AQPS: Acceptance Qualifier Polarity Selection
804  ||||| ___________ BIT 10: AQSS[2:0]: Acceptance Qualifier Source Selection
805  |||||| __________ BIT 9:
806  ||||||| _________ BIT 8:
807  |||||||| ________ BIT 7: SWTERM: PCI Software Termination
808  ||||||||| _______ BIT 6: PSYNC: PCI Synchronization Control
809  |||||||||| ______ BIT 5: PPS: PCI Polarity Selection
810  ||||||||||| _____ BIT 4: PSS[4:0]: PCI Source Selection
811  |||||||||||| ____ BIT 3:
812  ||||||||||||| ___ BIT 2:
813  |||||||||||||| __ BIT 1:
814  ||||||||||||||| _ BIT 0:
815  |||||||||||||||| */
816 #define REG_PGxSPCIL 0b0000000000000000
817 
822 /*
823 
824  ________________ BIT 15: BPEN: PCI Bypass Enable
825  | _______________ BIT 14: BPSEL[2:0]: PCI Bypass Source Selection
826  || ______________ BIT 13:
827  ||| _____________ BIT 12:
828  |||| ____________ BIT 11: (unimplemented)
829  ||||| ___________ BIT 10: ACP[2:0]: PCI Acceptance Criteria Selection
830  |||||| __________ BIT 9:
831  ||||||| _________ BIT 8:
832  |||||||| ________ BIT 7: SWPCI: Software PCI Control
833  ||||||||| _______ BIT 6: SWPCIM[1:0]: Software PCI Control Mode
834  |||||||||| ______ BIT 5:
835  ||||||||||| _____ BIT 4: LATMOD: PCI SR Latch Mode
836  |||||||||||| ____ BIT 3: TQPS: Termination Qualifier Polarity Selection
837  ||||||||||||| ___ BIT 2: TQSS[2:0]: Termination Qualifier Source Selection
838  |||||||||||||| __ BIT 1:
839  ||||||||||||||| _ BIT 0:
840  |||||||||||||||| */
841 #define REG_PGxSPCIH 0b0000000000000000
842 
847 /*
848 
849  ________________ BIT 15: (unimplemented)
850  | _______________ BIT 14: (unimplemented)
851  || ______________ BIT 13: (unimplemented)
852  ||| _____________ BIT 12: (unimplemented)
853  |||| ____________ BIT 11: (unimplemented)
854  ||||| ___________ BIT 10: PWMPCI[2:0]: PWM Source for PCI Selection
855  |||||| __________ BIT 9:
856  ||||||| _________ BIT 8:
857  |||||||| ________ BIT 7: (unimplemented)
858  ||||||||| _______ BIT 6: (unimplemented)
859  |||||||||| ______ BIT 5: (unimplemented)
860  ||||||||||| _____ BIT 4: (unimplemented)
861  |||||||||||| ____ BIT 3: PHR: PWMxH Rising Edge Trigger Enable
862  ||||||||||||| ___ BIT 2: PHF: PWMxH Falling Edge Trigger Enable
863  |||||||||||||| __ BIT 1: PLR: PWMxL Rising Edge Trigger Enable
864  ||||||||||||||| _ BIT 0: PLF: PWMxL Falling Edge Trigger Enable
865  |||||||||||||||| */
866 #define REG_PGxLEBH 0b0000000000001000
867 
872 /* PGxLEBL: PWM GENERATOR x LEADING-EDGE BLANKING REGISTER LOW
873 
874  ________________ BIT 15: LEB[15:0]: Leading-Edge Blanking Period bits
875  | _______________ BIT 14:
876  || ______________ BIT 13:
877  ||| _____________ BIT 12:
878  |||| ____________ BIT 11:
879  ||||| ___________ BIT 10:
880  |||||| __________ BIT 9:
881  ||||||| _________ BIT 8:
882  |||||||| ________ BIT 7:
883  ||||||||| _______ BIT 6:
884  |||||||||| ______ BIT 5:
885  ||||||||||| _____ BIT 4:
886  |||||||||||| ____ BIT 3:
887  ||||||||||||| ___ BIT 2:
888  |||||||||||||| __ BIT 1:
889  ||||||||||||||| _ BIT 0:
890  |||||||||||||||| */
891 #define REG_PGxLEBL 0b0000000000000000
892 
897 /*
898 
899  ________________ BIT 15: PGxDCA[15:0]: PWM Generator x Duty Cycle Adjustment Register
900  | _______________ BIT 14:
901  || ______________ BIT 13:
902  ||| _____________ BIT 12:
903  |||| ____________ BIT 11:
904  ||||| ___________ BIT 10:
905  |||||| __________ BIT 9:
906  ||||||| _________ BIT 8:
907  |||||||| ________ BIT 7:
908  ||||||||| _______ BIT 6:
909  |||||||||| ______ BIT 5:
910  ||||||||||| _____ BIT 4:
911  |||||||||||| ____ BIT 3:
912  ||||||||||||| ___ BIT 2:
913  |||||||||||||| __ BIT 1:
914  ||||||||||||||| _ BIT 0:
915  |||||||||||||||| */
916 #define REG_PGxDCA 0b0000000000000000
917 
918 
919 #endif /* BUCK_CONVERTER_PERIPHERAL_CONFIGURATION_PWM_H */
920