Device analog output pin, register and interrupt vector assignments of phase current feedback signal(s) of the buck converter. More...

Collaboration diagram for Buck Converter:

#define	_BUCK_ISNS_ADCInterrupt _ADCAN0Interrupt
	ADC input assignments of phase current feedback signals. More...

#define	_BUCK_ISNS_ADCISR_IF _ADCAN0IF
	Interrupt Service Routine Flag Bit. More...

#define	BUCK_ISNS_ANSEL _ANSELA0
	GPIO analog function mode enable bit. More...

#define	BUCK_ISNS_ADCCORE 0U
	0=Dedicated Core #0, 1=Dedicated Core #1, 2=Shared ADC Core More...

#define	BUCK_ISNS_ADCIN 0U
	Analog input number (e.g. '5' for 'AN5') More...

#define	BUCK_ISNS_ALT_IN_SELECT 0b00
	Alternative Analog Input Selection (dedicated ADC cores only)) More...

#define	BUCK_ISNS_ADCBUF ADCBUF0
	ADC input buffer of this ADC channel. More...

#define	BUCK_ISNS_ADCTRIG PG1TRIGB
	Register used for trigger placement. More...

#define	BUCK_ISNS_ADCTRIG_PC PG1TRIGB
	Register used for trigger placement in peak current mode control. More...

#define	BUCK_ISNS_TRGSRC BUCK_PWM_TRGSRC_TRG2
	PWM1 (=PG1) Trigger 2 via PGxTRIGB. More...

#define	BUCK_ISNS_ACMPxIN 1U
	Analog comparator input selection (0=none, 1=CMPxA, 2=CMPxB, 3=CMPxC, 4=CMPxD) More...

Detailed Description

Device analog output pin, register and interrupt vector assignments of phase current feedback signal(s) of the buck converter.

Macro Definition Documentation

◆ _BUCK_ISNS_ADCInterrupt

#define _BUCK_ISNS_ADCInterrupt _ADCAN0Interrupt

ADC input assignments of phase current feedback signals.

In this section the ADC input channels, related ADC result buffers, trigger sources and interrupt vectors are defined. These settings allow the fast re-assignments of feedback signals in case of hardware changes. Interrupt Service Routine function name

Definition at line 731 of file dpsk3_hwdescr.h.

◆ _BUCK_ISNS_ADCISR_IF

#define _BUCK_ISNS_ADCISR_IF _ADCAN0IF

Interrupt Service Routine Flag Bit.

Definition at line 732 of file dpsk3_hwdescr.h.

◆ BUCK_ISNS_ACMPxIN

#define BUCK_ISNS_ACMPxIN 1U

Analog comparator input selection (0=none, 1=CMPxA, 2=CMPxB, 3=CMPxC, 4=CMPxD)

Definition at line 744 of file dpsk3_hwdescr.h.

◆ BUCK_ISNS_ADCBUF

#define BUCK_ISNS_ADCBUF ADCBUF0

ADC input buffer of this ADC channel.

Definition at line 738 of file dpsk3_hwdescr.h.

◆ BUCK_ISNS_ADCCORE

#define BUCK_ISNS_ADCCORE 0U

0=Dedicated Core #0, 1=Dedicated Core #1, 2=Shared ADC Core

Definition at line 735 of file dpsk3_hwdescr.h.

◆ BUCK_ISNS_ADCIN

#define BUCK_ISNS_ADCIN 0U

Analog input number (e.g. '5' for 'AN5')

Definition at line 736 of file dpsk3_hwdescr.h.

◆ BUCK_ISNS_ADCTRIG

#define BUCK_ISNS_ADCTRIG PG1TRIGB

Register used for trigger placement.

Definition at line 739 of file dpsk3_hwdescr.h.

◆ BUCK_ISNS_ADCTRIG_PC

#define BUCK_ISNS_ADCTRIG_PC PG1TRIGB

Register used for trigger placement in peak current mode control.

Definition at line 740 of file dpsk3_hwdescr.h.

◆ BUCK_ISNS_ALT_IN_SELECT

#define BUCK_ISNS_ALT_IN_SELECT 0b00

Alternative Analog Input Selection (dedicated ADC cores only))

Definition at line 737 of file dpsk3_hwdescr.h.

◆ BUCK_ISNS_ANSEL

#define BUCK_ISNS_ANSEL _ANSELA0

GPIO analog function mode enable bit.

Definition at line 734 of file dpsk3_hwdescr.h.

◆ BUCK_ISNS_TRGSRC

#define BUCK_ISNS_TRGSRC BUCK_PWM_TRGSRC_TRG2

PWM1 (=PG1) Trigger 2 via PGxTRIGB.

Definition at line 741 of file dpsk3_hwdescr.h.