PWM peripheral output pins, control signals and register assignments used to drive the buck converter. More...

Collaboration diagram for Buck Converter:

#define	BUCK_PWM_CHANNEL 1U
	PWM peripheral output pins, control signals and register assignments of converter phase #1. More...

#define	BUCK_PWM_GPIO_INSTANCE 1U
	Number indicating device port, where 0=Port RA, 0=Port RB, 0=Port RC, etc. More...

#define	BUCK_PWM_GPIO_PORT_PINH 14U
	Port Pin Number. More...

#define	BUCK_PWM_GPIO_PORT_PINL 15U
	Port Pin Number. More...

#define	BUCK_PWM_OUTPUT_SWAP false
	true = PWMxH is the leading PWM output, false = PWMxL is the leading PWM output More...

#define	BUCK_PWM_PDC PG1DC
	PWM Instance Duty Cycle Register. More...

#define	BUCK_PWMH_TRIS _TRISB14
	Device Port TRIS register. More...

#define	BUCK_PWMH_WR _LATB14
	Device Pin WRITE. More...

#define	BUCK_PWMH_RD _RB14
	Device Pin READ. More...

#define	BUCK_PWMH_RPx (uint8_t)46
	Device Pin output remappable pin number (RPx) More...

#define	BUCK_PWML_TRIS _TRISB15
	Device Port TRIS register. More...

#define	BUCK_PWML_WR _LATB15
	Device Pin WRITE. More...

#define	BUCK_PWML_RD _RB15
	Device Pin READ. More...

#define	BUCK_PWML_RPx (uint8_t)47
	Device Pin output remappable pin number (RPx) More...

#define	_BUCK_PWM_Interrupt _PWM1Interrupt
	PWM Interrupt Service Routine label. More...

#define	BUCK_PWM_IF _PWM1IF
	PWM Interrupt Flag Bit. More...

#define	BUCK_PWM_IE _PWM1IE
	PWM Interrupt Enable Bit. More...

#define	BUCK_PWM_IP _PWM1IP
	PWM Interrupt Priority. More...

#define	BUCK_PWM_TRGSRC_TRG1 0b00100
	PWM Trigger #1 Trigger Source of this channel. More...

#define	BUCK_PWM_TRGSRC_TRG2 0b00101
	PWM Trigger #2 Trigger Source of this channel. More...

#define	BUCK_PWM_PGxTRIGA PG1TRIGA
	PWM trigger register A. More...

#define	BUCK_PWM_PGxTRIGB PG1TRIGB
	PWM trigger register B. More...

#define	BUCK_PWM_PGxTRIGC PG1TRIGC
	PWM trigger register C. More...

#define	BUCK_PWM_ADTR1OFS 0U
	ADC Trigger 1 Offset: 0...31. More...

#define	BUCK_PWM_ADTR1PS 0U
	ADC Trigger 1 Postscaler: 0...31. More...

#define	BUCK_PWM_UPDREQ PG1STATbits.UPDREQ

Detailed Description

PWM peripheral output pins, control signals and register assignments used to drive the buck converter.

Macro Definition Documentation

◆ _BUCK_PWM_Interrupt

#define _BUCK_PWM_Interrupt _PWM1Interrupt

PWM Interrupt Service Routine label.

Definition at line 340 of file dpsk3_hwdescr.h.

◆ BUCK_PWM_ADTR1OFS

#define BUCK_PWM_ADTR1OFS 0U

ADC Trigger 1 Offset: 0...31.

Definition at line 350 of file dpsk3_hwdescr.h.

◆ BUCK_PWM_ADTR1PS

#define BUCK_PWM_ADTR1PS 0U

ADC Trigger 1 Postscaler: 0...31.

Definition at line 351 of file dpsk3_hwdescr.h.

◆ BUCK_PWM_CHANNEL

#define BUCK_PWM_CHANNEL 1U

PWM peripheral output pins, control signals and register assignments of converter phase #1.

Converter phase #1 uses a simple half-bridge to commutate the switch node. The signal source therefore only requires a single PWM generator instance to be configured in fixed frequency complementary mode with dead times. Additional PWM peripheral features are used by the firmware to respond to interrupts, trigger ADC conversions, control device output pins during startup and fault responses and to change timing settings on the fly.

Please review the device data sheet for details about register names and settings. PWM Instance Index (e.g. 1=PWM1, 2=PWM2, etc.)

Definition at line 324 of file dpsk3_hwdescr.h.

◆ BUCK_PWM_GPIO_INSTANCE

#define BUCK_PWM_GPIO_INSTANCE 1U

Number indicating device port, where 0=Port RA, 0=Port RB, 0=Port RC, etc.

Definition at line 325 of file dpsk3_hwdescr.h.

◆ BUCK_PWM_GPIO_PORT_PINH

#define BUCK_PWM_GPIO_PORT_PINH 14U

Port Pin Number.

Definition at line 326 of file dpsk3_hwdescr.h.

◆ BUCK_PWM_GPIO_PORT_PINL

#define BUCK_PWM_GPIO_PORT_PINL 15U

Port Pin Number.

Definition at line 327 of file dpsk3_hwdescr.h.

◆ BUCK_PWM_IE

#define BUCK_PWM_IE _PWM1IE

PWM Interrupt Enable Bit.

Definition at line 342 of file dpsk3_hwdescr.h.

◆ BUCK_PWM_IF

#define BUCK_PWM_IF _PWM1IF

PWM Interrupt Flag Bit.

Definition at line 341 of file dpsk3_hwdescr.h.

◆ BUCK_PWM_IP

#define BUCK_PWM_IP _PWM1IP

PWM Interrupt Priority.

Definition at line 343 of file dpsk3_hwdescr.h.

◆ BUCK_PWM_OUTPUT_SWAP

#define BUCK_PWM_OUTPUT_SWAP false

true = PWMxH is the leading PWM output, false = PWMxL is the leading PWM output

Definition at line 328 of file dpsk3_hwdescr.h.

◆ BUCK_PWM_PDC

#define BUCK_PWM_PDC PG1DC

PWM Instance Duty Cycle Register.

Definition at line 330 of file dpsk3_hwdescr.h.

◆ BUCK_PWM_PGxTRIGA

#define BUCK_PWM_PGxTRIGA PG1TRIGA

PWM trigger register A.

Definition at line 346 of file dpsk3_hwdescr.h.

◆ BUCK_PWM_PGxTRIGB

#define BUCK_PWM_PGxTRIGB PG1TRIGB

PWM trigger register B.

Definition at line 347 of file dpsk3_hwdescr.h.

◆ BUCK_PWM_PGxTRIGC

#define BUCK_PWM_PGxTRIGC PG1TRIGC

PWM trigger register C.

Definition at line 348 of file dpsk3_hwdescr.h.

◆ BUCK_PWM_TRGSRC_TRG1

#define BUCK_PWM_TRGSRC_TRG1 0b00100

PWM Trigger #1 Trigger Source of this channel.

Definition at line 344 of file dpsk3_hwdescr.h.

◆ BUCK_PWM_TRGSRC_TRG2

#define BUCK_PWM_TRGSRC_TRG2 0b00101

PWM Trigger #2 Trigger Source of this channel.

Definition at line 345 of file dpsk3_hwdescr.h.

◆ BUCK_PWM_UPDREQ

#define BUCK_PWM_UPDREQ PG1STATbits.UPDREQ

Definition at line 353 of file dpsk3_hwdescr.h.

◆ BUCK_PWMH_RD

#define BUCK_PWMH_RD _RB14

Device Pin READ.

Definition at line 333 of file dpsk3_hwdescr.h.

◆ BUCK_PWMH_RPx

#define BUCK_PWMH_RPx (uint8_t)46

Device Pin output remappable pin number (RPx)

Definition at line 334 of file dpsk3_hwdescr.h.

◆ BUCK_PWMH_TRIS

#define BUCK_PWMH_TRIS _TRISB14

Device Port TRIS register.

Definition at line 331 of file dpsk3_hwdescr.h.

◆ BUCK_PWMH_WR

#define BUCK_PWMH_WR _LATB14

Device Pin WRITE.

Definition at line 332 of file dpsk3_hwdescr.h.

◆ BUCK_PWML_RD

#define BUCK_PWML_RD _RB15

Device Pin READ.

Definition at line 337 of file dpsk3_hwdescr.h.

◆ BUCK_PWML_RPx

#define BUCK_PWML_RPx (uint8_t)47

Device Pin output remappable pin number (RPx)

Definition at line 338 of file dpsk3_hwdescr.h.

◆ BUCK_PWML_TRIS

#define BUCK_PWML_TRIS _TRISB15

Device Port TRIS register.

Definition at line 335 of file dpsk3_hwdescr.h.

◆ BUCK_PWML_WR

#define BUCK_PWML_WR _LATB15

Device Pin WRITE.

Definition at line 336 of file dpsk3_hwdescr.h.