Digital Power Starter Kit 3 Firmware
dsPIC33C Buck Converter Voltage Mode Control Example
dev_buck_ptemp_dac.h
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21 
22 /*
23  * File: dev_buck_ptemp_dac.h
24  * Author: M91406
25  * Comments: DAC Peripheral Special Function Register Configuration Template
26  * Revision history:
27  * 10/29/2020 1.0 initial release
28  */
29 
30 // This is a guard condition so that contents of this file are not included
31 // more than once.
32 #ifndef BUCK_CONVERTER_PERIPHERAL_CONFIGURATION_DAC_H
33 #define BUCK_CONVERTER_PERIPHERAL_CONFIGURATION_DAC_H
34 
35 #include <xc.h> // include processor files - each processor file is guarded.
36 #include <stdint.h> // include standard integer data types
37 #include <stdbool.h> // include standard boolean data types
38 #include <stddef.h> // include standard definition data types
39 
45 /* ********************************************************************************
46  * DAC / COMPARATOR / SLOPE COMPENSATION INSTANCE CONFIGURATION
47  * *******************************************************************************/
52 /*
53 
54  ________________ BIT 15: DACEN: Individual DACx Module Enable
55  | _______________ BIT 14: IRQM[1:0]: Interrupt Mode select
56  || ______________ BIT 13:
57  ||| _____________ BIT 12: (unimplemented)
58  |||| ____________ BIT 11: (unimplemented)
59  ||||| ___________ BIT 10: CBE: Comparator Blank Enable
60  |||||| __________ BIT 9: DACOEN: DACx Output Buffer Enable
61  ||||||| _________ BIT 8: FLTREN: Comparator Digital Filter Enable
62  |||||||| ________ BIT 7: CMPSTAT: Comparator Status
63  ||||||||| _______ BIT 6: CMPPOL: Comparator Output Polarity Control
64  |||||||||| ______ BIT 5: INSEL[2:0]: Comparator Input Source Select
65  ||||||||||| _____ BIT 4:
66  |||||||||||| ____ BIT 3:
67  ||||||||||||| ___ BIT 2: HYSPOL: Comparator Hysteresis Polarity Select
68  |||||||||||||| __ BIT 1: HYSSEL[1:0]: Comparator Hysteresis Select
69  ||||||||||||||| _ BIT 0:
70  |||||||||||||||| */
71 //#define REG_DACxCONL 0b0000010100000101 // Peak Current Mode Configuration
72 #define REG_DACxCONL 0b0000000000000000
73 
78 /*
79 
80  ________________ BIT 15: (unimplemented)
81  | _______________ BIT 14: (unimplemented)
82  || ______________ BIT 13: (unimplemented)
83  ||| _____________ BIT 12: (unimplemented)
84  |||| ____________ BIT 11: (unimplemented)
85  ||||| ___________ BIT 10: (unimplemented)
86  |||||| __________ BIT 9: TMCB[9:0]: DACx Leading-Edge Blanking bits
87  ||||||| _________ BIT 8:
88  |||||||| ________ BIT 7:
89  ||||||||| _______ BIT 6:
90  |||||||||| ______ BIT 5:
91  ||||||||||| _____ BIT 4:
92  |||||||||||| ____ BIT 3:
93  ||||||||||||| ___ BIT 2:
94  |||||||||||||| __ BIT 1:
95  ||||||||||||||| _ BIT 0:
96  |||||||||||||||| */
97 //#define REG_DACxCONH 0b0000010100000101 // Peak Current Mode Configuration
98 #define REG_DACxCONH 0b0000000000000000
99 
100 /* DACxCONH: DACx CONTROL REGISTER HIGH => Timing Register: User value will be set in code */
101 /* DACxCONL: DACx CONTROL REGISTER LOW => Timing Register: User value will be set in code */
102 
107 /* SLPxCONL: DACx SLOPE CONTROL REGISTER LOW
108 
109  ________________ BIT 15: HCFSEL[3:0]: Hysteretic Comparator Function Input Selection
110  | _______________ BIT 14:
111  || ______________ BIT 13:
112  ||| _____________ BIT 12:
113  |||| ____________ BIT 11: SLPSTOPA[3:0]: Slope Stop A Signal Selection
114  ||||| ___________ BIT 10:
115  |||||| __________ BIT 9:
116  ||||||| _________ BIT 8:
117  |||||||| ________ BIT 7: SLPSTOPB[3:0]: Slope Stop B Signal Selection
118  ||||||||| _______ BIT 6:
119  |||||||||| ______ BIT 5:
120  ||||||||||| _____ BIT 4:
121  |||||||||||| ____ BIT 3: SLPSTRT[3:0]: Slope Start Signal Selection
122  ||||||||||||| ___ BIT 2:
123  |||||||||||||| __ BIT 1:
124  ||||||||||||||| _ BIT 0:
125  |||||||||||||||| */
126 //#define REG_SLPxCONL 0b0000000100010001 // Peak Current Mode Configuration
127 #define REG_SLPxCONL 0b0000000000000000
128 
133 /*
134 
135  ________________ BIT 15: SLOPEN: Slope Function Enable/On
136  | _______________ BIT 14: (unimplemented)
137  || ______________ BIT 13: (unimplemented)
138  ||| _____________ BIT 12: (unimplemented)
139  |||| ____________ BIT 11: HME: Hysteretic Mode Enable bit
140  ||||| ___________ BIT 10: TWME: Triangle Wave Mode Enable
141  |||||| __________ BIT 9: PSE: Positive Slope Mode Enable
142  ||||||| _________ BIT 8: (unimplemented)
143  |||||||| ________ BIT 7: (unimplemented)
144  ||||||||| _______ BIT 6: (unimplemented)
145  |||||||||| ______ BIT 5: (unimplemented)
146  ||||||||||| _____ BIT 4: (unimplemented)
147  |||||||||||| ____ BIT 3: (unimplemented)
148  ||||||||||||| ___ BIT 2: (unimplemented)
149  |||||||||||||| __ BIT 1: (unimplemented)
150  ||||||||||||||| _ BIT 0: (unimplemented)
151  |||||||||||||||| */
152 //#define REG_SLPxCONH 0b1000000000000000 // Peak Current Mode Configuration
153 #define REG_SLPxCONH 0b0000000000000000
154 #endif /* BUCK_CONVERTER_PERIPHERAL_CONFIGURATION_DAC_H */
155