Digital Power Starter Kit 3 Firmware  DM330017-3, Rev.3.0
dsPIC33C Buck Converter Peak Current Mode Control Example
p33c_osc.h
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22 
23 
37 #ifndef MCAL_P33SMPS_OSCILLATOR_H
38 #define MCAL_P33SMPS_OSCILLATOR_H
39 
40 #include <xc.h> // include processor files - each processor file is guarded.
41 #include <stdint.h> // include standard integer types header file
42 #include <stdbool.h> // include standard boolean types header file
43 
44 #include "p33smps_devices.h" // DEVICES header to derive device-dependent properties
45 
46 
68 typedef enum CPU_SPEED_DEFAULTS_e
69 {
70  CPU_SPEED_20_MIPS = 20, // CPU Speed setting for 20 MIPS operation
71  CPU_SPEED_30_MIPS = 30, // CPU Speed setting for 30 MIPS operation
72  CPU_SPEED_40_MIPS = 40, // CPU Speed setting for 40 MIPS operation
73  CPU_SPEED_50_MIPS = 50, // CPU Speed setting for 50 MIPS operation
74  CPU_SPEED_60_MIPS = 60, // CPU Speed setting for 60 MIPS operation
75  CPU_SPEED_70_MIPS = 70, // CPU Speed setting for 70 MIPS operation
76  CPU_SPEED_80_MIPS = 80, // CPU Speed setting for 80 MIPS operation
77  CPU_SPEED_90_MIPS = 90, // CPU Speed setting for 90 MIPS operation
78  CPU_SPEED_100_MIPS = 100 // CPU Speed setting for 100 MIPS operation
79 } CPU_SPEED_DEFAULTS_t; // Default CPU speed settings
80 
81 
82 typedef enum AUX_PLL_DEFAULTS_e
83 {
84  AFPLLO_100_MHZ = 100, // Auxiliary PLL output frequency of 500 MHz
85  AFPLLO_200_MHZ = 200, // Auxiliary PLL output frequency of 500 MHz
86  AFPLLO_300_MHZ = 300, // Auxiliary PLL output frequency of 500 MHz
87  AFPLLO_400_MHZ = 400, // Auxiliary PLL output frequency of 500 MHz
88  AFPLLO_500_MHZ = 500, // Auxiliary PLL output frequency of 500 MHz (Default for high resolution PWM)
89  AFPLLO_600_MHZ = 600, // Auxiliary PLL output frequency of 600 MHz
90  AFPLLO_700_MHZ = 700, // Auxiliary PLL output frequency of 700 MHz
91  AFPLLO_800_MHZ = 800 // Auxiliary PLL output frequency of 800 MHz
92 } AUX_PLL_DEFAULTS_t; // Default Auxiliary PLL output frequency settings
93 
94 
95 
125 typedef struct OSCILLATOR_SYSTEM_FREQUENCIES_s {
126  volatile uint32_t frc; // Internal fast RC oscillator frequency incl. tuning
127  volatile uint32_t fpri; // External primary oscillator frequency
128  volatile uint32_t fclk; // Clock frequency (external or internal oscillator frequency)
129  volatile uint32_t fosc; // Oscillator frequency
130  volatile uint32_t fcy; // CPU click frequency (instruction frequency = MIPS incl. DOZE divider)
131  volatile uint32_t fp; // Peripheral bus clock frequency
132  volatile uint32_t fpllo; // PLL output frequency
133  volatile uint32_t fvco; // PLL VCO frequency output incl. divider
134  volatile float tp; // Peripheral clock period
135  volatile float tcy; // CPU clock period
136  volatile uint32_t afpllo; // APLL output frequency
137  volatile uint32_t afvco; // APLL VCO frequency output incl. divider
138 }OSCILLATOR_SYSTEM_FREQUENCIES_t;
139 
140 
141 /* FRC oscillator settings and tuning */
142 #if defined (__P33SMPS_CH__)
143 
144  #define FRCTUN_MIN -32 // minimum tuning value
145  #define FRCTUN_MAX 31 // maximum tuning value
146  #define OSC_FRC_FREQ 8000000 // Frequency of the internal oscillator in [Hz]
147  #define OSC_FRC_TUN 0 // <OSCTUN> FRC Oscillator Tuning Rregister default value
148  #define OSC_TUN_STEP_PERCENTAGE 0.00047 // Oscillator frequency step size of <OSCTUN>
149 
150 #elif defined (__P33SMPS_CK__)
151 
152  #define FRCTUN_MIN -32 // minimum tuning value
153  #define FRCTUN_MAX 31 // maximum tuning value
154  #define OSC_FRC_FREQ 8000000 // Frequency of the internal oscillator in [Hz]
155  #define OSC_FRC_TUN 0 // <OSCTUN> FRC Oscillator Tuning Rregister value
156  #define OSC_TUN_STEP_PERCENTAGE 0.00047 // Oscillator frequency step size of <OSCTUN>
157 
158 #else
159  #pragma message "error: === selected device family not supported by oscillator mcal driver library ==="
160 #endif
161 
162 #define OSC_TUN_STEP_FREQUENCY (volatile int32_t)(OSC_FRC_FREQ * OSC_TUN_STEP_PERCENTAGE)
163 
164 /* ***************************************************************************************
165  * BASIC DEFINES
166  * **************************************************************************************/
167 
168 /* ===========================================================================
169  * OSCCON: OSCILLATOR CONTROL REGISTER
170  * ===========================================================================*/
171 
172 #define REG_OSCCON_VALID_DATA_WRITE_MASK 0x0789
173 #define REG_OSCCON_VALID_DATA_READ_MASK 0x77A9
174 
175 #define REG_OSCCON_OSWEN_REQUEST_SWITCH 0b0000000000001000
176 #define REG_OSCCON_OSWEN_SWITCH_COMPLETE 0b0000000000000000
177 
178 typedef enum {
179  OSCCON_OSWEN_REQUEST_SWITCH = 0b1, // Requests oscillator switch to the selection specified by the NOSC<2:0> bits
180  OSCCON_OSWEN_SWITCH_COMPLETE = 0b0 // Oscillator switch is complete
181 } OSCCON_OSWEN_e; // Oscillator Switch Enable bit
182 
183 #define REG_OSCCON_CF_CLKSTAT_FAIL 0b0000000000001000
184 #define REG_OSCCON_CF_CLKSTAT_OK 0b0000000000000000
185 
186 typedef enum {
187  OSCCON_CF_CLKSTAT_FAIL = 0b1, // FSCM has detected a clock failure
188  OSCCON_CF_CLKSTAT_OK = 0b0 // FSCM has not detected a clock failure
189 } OSCCON_CF_e; // Clock Fail Detect bit
190 
191 #define REG_OSCCON_LOCK_PLL_LOCKED 0b0000000000100000
192 #define REG_OSCCON_LOCK_PLL_UNLOCKED 0b0000000000000000
193 
194 typedef enum {
195  OSCCON_LOCK_PLL_LOCKED = 0b1, // Indicates that PLL is in lock or PLL start-up timer is satisfied
196  OSCCON_LOCK_PLL_UNLOCKED = 0b0 // Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled
197 } OSCCON_LOCK_e; // PLL Lock Status bit (read-only)
198 
199 #define REG_OSCCON_CLKLOCK_LOCKED 0b0000000010000000
200 #define REG_OSCCON_CLKLOCK_UNLOCKED 0b0000000000000000
201 
202 typedef enum {
203  OSCCON_CLKLOCK_LOCKED = 0b1, // If (FCKSM0 = 1), then clock and PLL configurations are locked; if (FCKSM0 = 0), then clock and PLL configurations may be modified
204  OSCCON_CLKLOCK_UNLOCKED = 0b0 // Clock and PLL selections are not locked, configurations may be modified
205 } OSCCON_CLKLOCK_e; // Clock Lock Enable bit
206 
207 #define REG_OSCCON_NOSC_FRCDIVN 0b0000011100000000
208 #define REG_OSCCON_NOSC_BFRC 0b0000011000000000
209 #define REG_OSCCON_NOSC_LPRC 0b0000010100000000
210 #define REG_OSCCON_NOSC_PRIPLL 0b0000001100000000
211 #define REG_OSCCON_NOSC_PRI 0b0000001000000000
212 #define REG_OSCCON_NOSC_FRCPLL 0b0000000100000000
213 #define REG_OSCCON_NOSC_FRC 0b0000000000000000
214 
215 #define REG_OSCCON_COSC_FRCDIVN 0b0111000000000000
216 #define REG_OSCCON_COSC_BFRC 0b0110000000000000
217 #define REG_OSCCON_COSC_LPRC 0b0101000000000000
218 #define REG_OSCCON_COSC_PRIPLL 0b0011000000000000
219 #define REG_OSCCON_COSC_PRI 0b0010000000000000
220 #define REG_OSCCON_COSC_FRCPLL 0b0001000000000000
221 #define REG_OSCCON_COSC_FRC 0b0000000000000000
222 
223 
224 typedef enum {
225  OSCCON_xOSC_FRC = 0b000, // Fast RC Oscillator, no PLL
226  OSCCON_xOSC_FRCPLL = 0b001, // Fast RC Oscillator with PLL
227  OSCCON_xOSC_PRI = 0b010, // Primary Oscillator (EC, XT, HS), no PLL
228  OSCCON_xOSC_PRIPLL = 0b011, // Primary Oscillator (EC, XT, HS) with PLL
229  OSCCON_xOSC_LPRC = 0b101, // Low Power Oscillator for Idle/Sleep Mode
230  OSCCON_xOSC_BFRC = 0b110, // Backup Fast RC Oscillator
231  OSCCON_xOSC_FRCDIVN = 0b111 // Fast RC Oscillator with variable Divider
232 } OSCCON_xOSC_TYPE_e ;// Oscillator Type Selection bits
233 
234 typedef struct {
235  volatile OSCCON_OSWEN_e OSWEN : 1; // Oscillator Switch Enable bit
236  volatile unsigned : 2; // reserved
237  volatile OSCCON_CF_e CF : 1; // Clock Fail Detect bit
238  volatile unsigned : 1; // reserved
239  volatile OSCCON_LOCK_e LOCK : 1; // PLL Lock Status bit (read only)
240  volatile unsigned : 1; // reserved
241  volatile OSCCON_CLKLOCK_e CLKLOCK : 1; // Clock Lock Enable bit
242  volatile OSCCON_xOSC_TYPE_e NOSC : 3; // New Oscillator Selection bits
243  volatile unsigned : 1; // reserved
244  volatile OSCCON_xOSC_TYPE_e COSC : 3; // Current Oscillator Selection bits (read only)
245 
246 } __attribute__((packed)) OSCCON_t; // Oscillator configuration register
247 
248 typedef union {
249  volatile uint16_t value;
250  volatile OSCCON_t OSCCON;
251 } REGBLK_OSCCON_CONFIG_t;
252 
253 /* ===========================================================================
254  * CLKDIV: CLOCK DIVIDER REGISTER
255  * ===========================================================================*/
256 
257 #if defined (__P33SMPS_CH__) || defined (__P33SMPS_CK__)
258 
259 #define REG_CLKDIV_VALID_DATA_WRITE_MASK 0xFF0F
260 #define REG_CLKDIV_VALID_DATA_READ_MASK 0xFF0F
261 
262 #define REG_CLKDIV_PLLPRE_DIV_MASK 0b0000000000001111
263 #define REG_CLKDIV_PLLPRE_DIVIDER_N1(x) {(x & REG_CLKDIV_PLLPRE_DIV_MASK)}
264 
265 typedef enum {
266  CLKDIV_PLLDIV_N1_1 = 0b000001, // PLL Input Clock Divider Setting 1:1
267  CLKDIV_PLLDIV_N1_2 = 0b000010, // PLL Input Clock Divider Setting 1:2
268  CLKDIV_PLLDIV_N1_3 = 0b000011, // PLL Input Clock Divider Setting 1:3
269  CLKDIV_PLLDIV_N1_4 = 0b000100, // PLL Input Clock Divider Setting 1:4
270  CLKDIV_PLLDIV_N1_5 = 0b000101, // PLL Input Clock Divider Setting 1:5
271  CLKDIV_PLLDIV_N1_6 = 0b000110, // PLL Input Clock Divider Setting 1:6
272  CLKDIV_PLLDIV_N1_7 = 0b000111, // PLL Input Clock Divider Setting 1:7
273  CLKDIV_PLLDIV_N1_8 = 0b001000 // PLL Input Clock Divider Setting 1:8
274 } CLKDIV_PLLPRE_e; // PLL Phase Detector Input Divider Select bits (also denoted as ?N1?, PLL prescaler)
275 
276 #else
277  #pragma message "error: === selected device family is not supported by oscillator mcal library ==="
278 #endif
279 
280 #define REG_CLKDIV_DOZE_DIV_1 0b0000000000000000
281 #define REG_CLKDIV_DOZE_DIV_2 0b0001000000000000
282 #define REG_CLKDIV_DOZE_DIV_4 0b0010000000000000
283 #define REG_CLKDIV_DOZE_DIV_8 0b0011000000000000
284 #define REG_CLKDIV_DOZE_DIV_16 0b0100000000000000
285 #define REG_CLKDIV_DOZE_DIV_32 0b0101000000000000
286 #define REG_CLKDIV_DOZE_DIV_64 0b0110000000000000
287 #define REG_CLKDIV_DOZE_DIV_128 0b0111000000000000
288 
289 typedef enum {
290  CLKDIV_DOZE_DIV_1 = 0b000, // FCY Clock Divider Setting 1:1
291  CLKDIV_DOZE_DIV_2 = 0b001, // FCY Clock Divider Setting 1:2
292  CLKDIV_DOZE_DIV_4 = 0b010, // FCY Clock Divider Setting 1:4
293  CLKDIV_DOZE_DIV_8 = 0b011, // FCY Clock Divider Setting 1:8
294  CLKDIV_DOZE_DIV_16 = 0b100, // FCY Clock Divider Setting 1:16
295  CLKDIV_DOZE_DIV_32 = 0b101, // FCY Clock Divider Setting 1:32
296  CLKDIV_DOZE_DIV_64 = 0b110, // FCY Clock Divider Setting 1:64
297  CLKDIV_DOZE_DIV_128 = 0b111 // FCY Clock Divider Setting 1:128
298 } CLKDIV_DOZE_e; // Processor Clock Reduction Select bits
299 
300 #define REG_CLKDIV_DOZEN_ENABLED 0b0000100000000000
301 #define REG_CLKDIV_DOZEN_DISABLED 0b0000000000000000
302 
303 typedef enum {
304  CLKDIV_DOZEN_ENABLED = 0b1, // DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks
305  CLKDIV_DOZEN_DISABLED = 0b0 // Processor clock and peripheral clock ratio is forced to 1:1
306 } CLKDIV_DOZEN_e; // Doze Mode Enable bit
307 
308 #define REG_CLKDIV_FRCDIVN_256 0b0000011100000000
309 #define REG_CLKDIV_FRCDIVN_64 0b0000011000000000
310 #define REG_CLKDIV_FRCDIVN_32 0b0000010100000000
311 #define REG_CLKDIV_FRCDIVN_16 0b0000010000000000
312 #define REG_CLKDIV_FRCDIVN_8 0b0000001100000000
313 #define REG_CLKDIV_FRCDIVN_4 0b0000001000000000
314 #define REG_CLKDIV_FRCDIVN_2 0b0000000100000000
315 #define REG_CLKDIV_FRCDIVN_1 0b0000000000000000
316 
317 typedef enum CLKDIV_FRCDIVN_e {
318  CLKDIV_FRCDIVN_1 = 0b000, // Fast RC Oscillator Clock Divider Setting 1:1
319  CLKDIV_FRCDIVN_2 = 0b001, // Fast RC Oscillator Clock Divider Setting 1:2
320  CLKDIV_FRCDIVN_4 = 0b010, // Fast RC Oscillator Clock Divider Setting 1:4
321  CLKDIV_FRCDIVN_8 = 0b011, // Fast RC Oscillator Clock Divider Setting 1:8
322  CLKDIV_FRCDIVN_16 = 0b100, // Fast RC Oscillator Clock Divider Setting 1:16
323  CLKDIV_FRCDIVN_32 = 0b101, // Fast RC Oscillator Clock Divider Setting 1:32
324  CLKDIV_FRCDIVN_64 = 0b110, // Fast RC Oscillator Clock Divider Setting 1:64
325  CLKDIV_FRCDIVN_256 = 0b111 // Fast RC Oscillator Clock Divider Setting 1:256
326 } CLKDIV_FRCDIVN_t; // Internal Fast RC Oscillator Postscaler bits
327 
328 #define REG_CLKDIV_ROI_ENABLED 0b1000000000000000
329 #define REG_CLKDIV_ROI_DISABLED 0b0000000000000000
330 
331 typedef enum {
332  CLKDIV_ROI_ENABLED = 0b1, // Interrupts will clear the DOZEN bit and the processor clock, and the peripheral clock ratio is set to 1:1
333  CLKDIV_ROI_DISABLED = 0b0 // Interrupts have no effect on the DOZEN bit
334 } CLKDIV_ROI_e; // Recover on Interrupt bit
335 
336 typedef struct {
337  volatile CLKDIV_PLLPRE_e PLLPRE : 6; // PLL Phase Detector Input Divider Select bits (also denoted as ?N1?, PLL prescaler)
338  volatile unsigned : 2;
339  volatile enum CLKDIV_FRCDIVN_e FRCDIV : 3; // Internal Fast RC Oscillator Postscaler bits
340  volatile CLKDIV_DOZEN_e DOZEN : 1; // Doze Mode Enable bit
341  volatile CLKDIV_DOZE_e DOZE : 3; // Processor Clock Reduction Select bits
342  volatile CLKDIV_ROI_e ROI : 1; // Recover on Interrupt bit
343 } __attribute__((packed)) CLKDIV_t;
344 
345 typedef union {
346  volatile uint16_t value;
347  volatile CLKDIV_t CLKDIV;
348 } REGBLK_CLKDIV_CONFIG_t;
349 
350 
351 /* ===========================================================================
352  * PLLFBD: PLL FEEDBACK DIVIDER REGISTER
353  * ===========================================================================*/
354 
355 #if defined (__P33SMPS_CH__) || defined (__P33SMPS_CK__)
356 
357 #define REG_PLLFBD_VALID_DATA_WRITE_MASK 0x00FF
358 #define REG_PLLFBD_VALID_DATA_READ_MASK 0x00FF
359 
360 #define REG_PLLFBD_PLLFBDIV_M_MASK 0b0000000011111111
361 #define REG_PLLFBD_MULTIPLIER_M(x) {(x & REG_PLLFBD_PLLFBDIV_M_MASK)}
362 
363 typedef enum {
364  PLLFBD_PLLFBDIV_M_16 = 0b00010000, // PLL Input Clock Multiplier Setting x16
365  PLLFBD_PLLFBDIV_M_17 = 0b00010001, // PLL Input Clock Multiplier Setting x17
366  PLLFBD_PLLFBDIV_M_18 = 0b00010010, // PLL Input Clock Multiplier Setting x18
367  PLLFBD_PLLFBDIV_M_19 = 0b00010011, // PLL Input Clock Multiplier Setting x19
368  PLLFBD_PLLFBDIV_M_20 = 0b00010100, // PLL Input Clock Multiplier Setting x20
369  PLLFBD_PLLFBDIV_M_21 = 0b00010101, // PLL Input Clock Multiplier Setting x21
370  PLLFBD_PLLFBDIV_M_22 = 0b00010110, // PLL Input Clock Multiplier Setting x22
371  PLLFBD_PLLFBDIV_M_23 = 0b00010111, // PLL Input Clock Multiplier Setting x23
372  PLLFBD_PLLFBDIV_M_24 = 0b00011000, // PLL Input Clock Multiplier Setting x24
373  PLLFBD_PLLFBDIV_M_25 = 0b00011001, // PLL Input Clock Multiplier Setting x25
374  PLLFBD_PLLFBDIV_M_26 = 0b00011010, // PLL Input Clock Multiplier Setting x26
375  PLLFBD_PLLFBDIV_M_27 = 0b00011011, // PLL Input Clock Multiplier Setting x27
376  PLLFBD_PLLFBDIV_M_28 = 0b00011100, // PLL Input Clock Multiplier Setting x28
377  PLLFBD_PLLFBDIV_M_29 = 0b00011101, // PLL Input Clock Multiplier Setting x29
378  PLLFBD_PLLFBDIV_M_30 = 0b00011110, // PLL Input Clock Multiplier Setting x30
379  PLLFBD_PLLFBDIV_M_31 = 0b00011111, // PLL Input Clock Multiplier Setting x31
380  PLLFBD_PLLFBDIV_M_32 = 0b00100000, // PLL Input Clock Multiplier Setting x32
381  PLLFBD_PLLFBDIV_M_33 = 0b00100001, // PLL Input Clock Multiplier Setting x33
382  PLLFBD_PLLFBDIV_M_34 = 0b00100010, // PLL Input Clock Multiplier Setting x34
383  PLLFBD_PLLFBDIV_M_35 = 0b00100011, // PLL Input Clock Multiplier Setting x35
384  PLLFBD_PLLFBDIV_M_36 = 0b00100100, // PLL Input Clock Multiplier Setting x36
385  PLLFBD_PLLFBDIV_M_37 = 0b00100101, // PLL Input Clock Multiplier Setting x37
386  PLLFBD_PLLFBDIV_M_38 = 0b00100110, // PLL Input Clock Multiplier Setting x38
387  PLLFBD_PLLFBDIV_M_39 = 0b00100111, // PLL Input Clock Multiplier Setting x39
388  PLLFBD_PLLFBDIV_M_40 = 0b00101000, // PLL Input Clock Multiplier Setting x40
389  PLLFBD_PLLFBDIV_M_41 = 0b00101001, // PLL Input Clock Multiplier Setting x41
390  PLLFBD_PLLFBDIV_M_42 = 0b00101010, // PLL Input Clock Multiplier Setting x42
391  PLLFBD_PLLFBDIV_M_43 = 0b00101011, // PLL Input Clock Multiplier Setting x43
392  PLLFBD_PLLFBDIV_M_44 = 0b00101100, // PLL Input Clock Multiplier Setting x44
393  PLLFBD_PLLFBDIV_M_45 = 0b00101101, // PLL Input Clock Multiplier Setting x45
394  PLLFBD_PLLFBDIV_M_46 = 0b00101110, // PLL Input Clock Multiplier Setting x46
395  PLLFBD_PLLFBDIV_M_47 = 0b00101111, // PLL Input Clock Multiplier Setting x47
396  PLLFBD_PLLFBDIV_M_48 = 0b00110000, // PLL Input Clock Multiplier Setting x48
397  PLLFBD_PLLFBDIV_M_49 = 0b00110001, // PLL Input Clock Multiplier Setting x49
398  PLLFBD_PLLFBDIV_M_50 = 0b00110010, // PLL Input Clock Multiplier Setting x50
399  PLLFBD_PLLFBDIV_M_51 = 0b00110011, // PLL Input Clock Multiplier Setting x51
400  PLLFBD_PLLFBDIV_M_52 = 0b00110100, // PLL Input Clock Multiplier Setting x52
401  PLLFBD_PLLFBDIV_M_53 = 0b00110101, // PLL Input Clock Multiplier Setting x53
402  PLLFBD_PLLFBDIV_M_54 = 0b00110110, // PLL Input Clock Multiplier Setting x54
403  PLLFBD_PLLFBDIV_M_55 = 0b00110111, // PLL Input Clock Multiplier Setting x55
404  PLLFBD_PLLFBDIV_M_56 = 0b00111000, // PLL Input Clock Multiplier Setting x56
405  PLLFBD_PLLFBDIV_M_57 = 0b00111001, // PLL Input Clock Multiplier Setting x57
406  PLLFBD_PLLFBDIV_M_58 = 0b00111010, // PLL Input Clock Multiplier Setting x58
407  PLLFBD_PLLFBDIV_M_59 = 0b00111011, // PLL Input Clock Multiplier Setting x59
408  PLLFBD_PLLFBDIV_M_60 = 0b00111100, // PLL Input Clock Multiplier Setting x60
409  PLLFBD_PLLFBDIV_M_61 = 0b00111101, // PLL Input Clock Multiplier Setting x61
410  PLLFBD_PLLFBDIV_M_62 = 0b00111110, // PLL Input Clock Multiplier Setting x62
411  PLLFBD_PLLFBDIV_M_63 = 0b00111111, // PLL Input Clock Multiplier Setting x63
412  PLLFBD_PLLFBDIV_M_64 = 0b01000000, // PLL Input Clock Multiplier Setting x64
413  PLLFBD_PLLFBDIV_M_65 = 0b01000001, // PLL Input Clock Multiplier Setting x65
414  PLLFBD_PLLFBDIV_M_66 = 0b01000010, // PLL Input Clock Multiplier Setting x66
415  PLLFBD_PLLFBDIV_M_67 = 0b01000011, // PLL Input Clock Multiplier Setting x67
416  PLLFBD_PLLFBDIV_M_68 = 0b01000100, // PLL Input Clock Multiplier Setting x68
417  PLLFBD_PLLFBDIV_M_69 = 0b01000101, // PLL Input Clock Multiplier Setting x69
418  PLLFBD_PLLFBDIV_M_70 = 0b01000110, // PLL Input Clock Multiplier Setting x70
419  PLLFBD_PLLFBDIV_M_71 = 0b01000111, // PLL Input Clock Multiplier Setting x71
420  PLLFBD_PLLFBDIV_M_72 = 0b01001000, // PLL Input Clock Multiplier Setting x72
421  PLLFBD_PLLFBDIV_M_73 = 0b01001001, // PLL Input Clock Multiplier Setting x73
422  PLLFBD_PLLFBDIV_M_74 = 0b01001010, // PLL Input Clock Multiplier Setting x74
423  PLLFBD_PLLFBDIV_M_75 = 0b01001011, // PLL Input Clock Multiplier Setting x75
424  PLLFBD_PLLFBDIV_M_76 = 0b01001100, // PLL Input Clock Multiplier Setting x76
425  PLLFBD_PLLFBDIV_M_77 = 0b01001101, // PLL Input Clock Multiplier Setting x77
426  PLLFBD_PLLFBDIV_M_78 = 0b01001110, // PLL Input Clock Multiplier Setting x78
427  PLLFBD_PLLFBDIV_M_79 = 0b01001111, // PLL Input Clock Multiplier Setting x79
428  PLLFBD_PLLFBDIV_M_80 = 0b01010000, // PLL Input Clock Multiplier Setting x80
429  PLLFBD_PLLFBDIV_M_81 = 0b01010001, // PLL Input Clock Multiplier Setting x81
430  PLLFBD_PLLFBDIV_M_82 = 0b01010010, // PLL Input Clock Multiplier Setting x82
431  PLLFBD_PLLFBDIV_M_83 = 0b01010011, // PLL Input Clock Multiplier Setting x83
432  PLLFBD_PLLFBDIV_M_84 = 0b01010100, // PLL Input Clock Multiplier Setting x84
433  PLLFBD_PLLFBDIV_M_85 = 0b01010101, // PLL Input Clock Multiplier Setting x85
434  PLLFBD_PLLFBDIV_M_86 = 0b01010110, // PLL Input Clock Multiplier Setting x86
435  PLLFBD_PLLFBDIV_M_87 = 0b01010111, // PLL Input Clock Multiplier Setting x87
436  PLLFBD_PLLFBDIV_M_88 = 0b01011000, // PLL Input Clock Multiplier Setting x88
437  PLLFBD_PLLFBDIV_M_89 = 0b01011001, // PLL Input Clock Multiplier Setting x89
438  PLLFBD_PLLFBDIV_M_90 = 0b01011010, // PLL Input Clock Multiplier Setting x90
439  PLLFBD_PLLFBDIV_M_91 = 0b01011011, // PLL Input Clock Multiplier Setting x91
440  PLLFBD_PLLFBDIV_M_92 = 0b01011100, // PLL Input Clock Multiplier Setting x92
441  PLLFBD_PLLFBDIV_M_93 = 0b01011101, // PLL Input Clock Multiplier Setting x93
442  PLLFBD_PLLFBDIV_M_94 = 0b01011110, // PLL Input Clock Multiplier Setting x94
443  PLLFBD_PLLFBDIV_M_95 = 0b01011111, // PLL Input Clock Multiplier Setting x95
444  PLLFBD_PLLFBDIV_M_96 = 0b01100000, // PLL Input Clock Multiplier Setting x96
445  PLLFBD_PLLFBDIV_M_97 = 0b01100001, // PLL Input Clock Multiplier Setting x97
446  PLLFBD_PLLFBDIV_M_98 = 0b01100010, // PLL Input Clock Multiplier Setting x98
447  PLLFBD_PLLFBDIV_M_99 = 0b01100011, // PLL Input Clock Multiplier Setting x99
448  PLLFBD_PLLFBDIV_M_100 = 0b01100100, // PLL Input Clock Multiplier Setting x100
449  PLLFBD_PLLFBDIV_M_101 = 0b01100101, // PLL Input Clock Multiplier Setting x101
450  PLLFBD_PLLFBDIV_M_102 = 0b01100110, // PLL Input Clock Multiplier Setting x102
451  PLLFBD_PLLFBDIV_M_103 = 0b01100111, // PLL Input Clock Multiplier Setting x103
452  PLLFBD_PLLFBDIV_M_104 = 0b01101000, // PLL Input Clock Multiplier Setting x104
453  PLLFBD_PLLFBDIV_M_105 = 0b01101001, // PLL Input Clock Multiplier Setting x105
454  PLLFBD_PLLFBDIV_M_106 = 0b01101010, // PLL Input Clock Multiplier Setting x106
455  PLLFBD_PLLFBDIV_M_107 = 0b01101011, // PLL Input Clock Multiplier Setting x107
456  PLLFBD_PLLFBDIV_M_108 = 0b01101100, // PLL Input Clock Multiplier Setting x108
457  PLLFBD_PLLFBDIV_M_109 = 0b01101101, // PLL Input Clock Multiplier Setting x109
458  PLLFBD_PLLFBDIV_M_110 = 0b01101110, // PLL Input Clock Multiplier Setting x110
459  PLLFBD_PLLFBDIV_M_111 = 0b01101111, // PLL Input Clock Multiplier Setting x111
460  PLLFBD_PLLFBDIV_M_112 = 0b01110000, // PLL Input Clock Multiplier Setting x112
461  PLLFBD_PLLFBDIV_M_113 = 0b01110001, // PLL Input Clock Multiplier Setting x113
462  PLLFBD_PLLFBDIV_M_114 = 0b01110010, // PLL Input Clock Multiplier Setting x114
463  PLLFBD_PLLFBDIV_M_115 = 0b01110011, // PLL Input Clock Multiplier Setting x115
464  PLLFBD_PLLFBDIV_M_116 = 0b01110100, // PLL Input Clock Multiplier Setting x116
465  PLLFBD_PLLFBDIV_M_117 = 0b01110101, // PLL Input Clock Multiplier Setting x117
466  PLLFBD_PLLFBDIV_M_118 = 0b01110110, // PLL Input Clock Multiplier Setting x118
467  PLLFBD_PLLFBDIV_M_119 = 0b01110111, // PLL Input Clock Multiplier Setting x119
468  PLLFBD_PLLFBDIV_M_120 = 0b01111000, // PLL Input Clock Multiplier Setting x120
469  PLLFBD_PLLFBDIV_M_121 = 0b01111001, // PLL Input Clock Multiplier Setting x121
470  PLLFBD_PLLFBDIV_M_122 = 0b01111010, // PLL Input Clock Multiplier Setting x122
471  PLLFBD_PLLFBDIV_M_123 = 0b01111011, // PLL Input Clock Multiplier Setting x123
472  PLLFBD_PLLFBDIV_M_124 = 0b01111100, // PLL Input Clock Multiplier Setting x124
473  PLLFBD_PLLFBDIV_M_125 = 0b01111101, // PLL Input Clock Multiplier Setting x125
474  PLLFBD_PLLFBDIV_M_126 = 0b01111110, // PLL Input Clock Multiplier Setting x126
475  PLLFBD_PLLFBDIV_M_127 = 0b01111111, // PLL Input Clock Multiplier Setting x127
476  PLLFBD_PLLFBDIV_M_128 = 0b10000000, // PLL Input Clock Multiplier Setting x128
477  PLLFBD_PLLFBDIV_M_129 = 0b10000001, // PLL Input Clock Multiplier Setting x129
478  PLLFBD_PLLFBDIV_M_130 = 0b10000010, // PLL Input Clock Multiplier Setting x130
479  PLLFBD_PLLFBDIV_M_131 = 0b10000011, // PLL Input Clock Multiplier Setting x131
480  PLLFBD_PLLFBDIV_M_132 = 0b10000100, // PLL Input Clock Multiplier Setting x132
481  PLLFBD_PLLFBDIV_M_133 = 0b10000101, // PLL Input Clock Multiplier Setting x133
482  PLLFBD_PLLFBDIV_M_134 = 0b10000110, // PLL Input Clock Multiplier Setting x134
483  PLLFBD_PLLFBDIV_M_135 = 0b10000111, // PLL Input Clock Multiplier Setting x135
484  PLLFBD_PLLFBDIV_M_136 = 0b10001000, // PLL Input Clock Multiplier Setting x136
485  PLLFBD_PLLFBDIV_M_137 = 0b10001001, // PLL Input Clock Multiplier Setting x137
486  PLLFBD_PLLFBDIV_M_138 = 0b10001010, // PLL Input Clock Multiplier Setting x138
487  PLLFBD_PLLFBDIV_M_139 = 0b10001011, // PLL Input Clock Multiplier Setting x139
488  PLLFBD_PLLFBDIV_M_140 = 0b10001100, // PLL Input Clock Multiplier Setting x140
489  PLLFBD_PLLFBDIV_M_141 = 0b10001101, // PLL Input Clock Multiplier Setting x141
490  PLLFBD_PLLFBDIV_M_142 = 0b10001110, // PLL Input Clock Multiplier Setting x142
491  PLLFBD_PLLFBDIV_M_143 = 0b10001111, // PLL Input Clock Multiplier Setting x143
492  PLLFBD_PLLFBDIV_M_144 = 0b10010000, // PLL Input Clock Multiplier Setting x144
493  PLLFBD_PLLFBDIV_M_145 = 0b10010001, // PLL Input Clock Multiplier Setting x145
494  PLLFBD_PLLFBDIV_M_146 = 0b10010010, // PLL Input Clock Multiplier Setting x146
495  PLLFBD_PLLFBDIV_M_147 = 0b10010011, // PLL Input Clock Multiplier Setting x147
496  PLLFBD_PLLFBDIV_M_148 = 0b10010100, // PLL Input Clock Multiplier Setting x148
497  PLLFBD_PLLFBDIV_M_149 = 0b10010101, // PLL Input Clock Multiplier Setting x149
498  PLLFBD_PLLFBDIV_M_150 = 0b10010110, // PLL Input Clock Multiplier Setting x150
499  PLLFBD_PLLFBDIV_M_151 = 0b10010111, // PLL Input Clock Multiplier Setting x151
500  PLLFBD_PLLFBDIV_M_152 = 0b10011000, // PLL Input Clock Multiplier Setting x152
501  PLLFBD_PLLFBDIV_M_153 = 0b10011001, // PLL Input Clock Multiplier Setting x153
502  PLLFBD_PLLFBDIV_M_154 = 0b10011010, // PLL Input Clock Multiplier Setting x154
503  PLLFBD_PLLFBDIV_M_155 = 0b10011011, // PLL Input Clock Multiplier Setting x155
504  PLLFBD_PLLFBDIV_M_156 = 0b10011100, // PLL Input Clock Multiplier Setting x156
505  PLLFBD_PLLFBDIV_M_157 = 0b10011101, // PLL Input Clock Multiplier Setting x157
506  PLLFBD_PLLFBDIV_M_158 = 0b10011110, // PLL Input Clock Multiplier Setting x158
507  PLLFBD_PLLFBDIV_M_159 = 0b10011111, // PLL Input Clock Multiplier Setting x159
508  PLLFBD_PLLFBDIV_M_160 = 0b10100000, // PLL Input Clock Multiplier Setting x160
509  PLLFBD_PLLFBDIV_M_161 = 0b10100001, // PLL Input Clock Multiplier Setting x161
510  PLLFBD_PLLFBDIV_M_162 = 0b10100010, // PLL Input Clock Multiplier Setting x162
511  PLLFBD_PLLFBDIV_M_163 = 0b10100011, // PLL Input Clock Multiplier Setting x163
512  PLLFBD_PLLFBDIV_M_164 = 0b10100100, // PLL Input Clock Multiplier Setting x164
513  PLLFBD_PLLFBDIV_M_165 = 0b10100101, // PLL Input Clock Multiplier Setting x165
514  PLLFBD_PLLFBDIV_M_166 = 0b10100110, // PLL Input Clock Multiplier Setting x166
515  PLLFBD_PLLFBDIV_M_167 = 0b10100111, // PLL Input Clock Multiplier Setting x167
516  PLLFBD_PLLFBDIV_M_168 = 0b10101000, // PLL Input Clock Multiplier Setting x168
517  PLLFBD_PLLFBDIV_M_169 = 0b10101001, // PLL Input Clock Multiplier Setting x169
518  PLLFBD_PLLFBDIV_M_170 = 0b10101010, // PLL Input Clock Multiplier Setting x170
519  PLLFBD_PLLFBDIV_M_171 = 0b10101011, // PLL Input Clock Multiplier Setting x171
520  PLLFBD_PLLFBDIV_M_172 = 0b10101100, // PLL Input Clock Multiplier Setting x172
521  PLLFBD_PLLFBDIV_M_173 = 0b10101101, // PLL Input Clock Multiplier Setting x173
522  PLLFBD_PLLFBDIV_M_174 = 0b10101110, // PLL Input Clock Multiplier Setting x174
523  PLLFBD_PLLFBDIV_M_175 = 0b10101111, // PLL Input Clock Multiplier Setting x175
524  PLLFBD_PLLFBDIV_M_176 = 0b10110000, // PLL Input Clock Multiplier Setting x176
525  PLLFBD_PLLFBDIV_M_177 = 0b10110001, // PLL Input Clock Multiplier Setting x177
526  PLLFBD_PLLFBDIV_M_178 = 0b10110010, // PLL Input Clock Multiplier Setting x178
527  PLLFBD_PLLFBDIV_M_179 = 0b10110011, // PLL Input Clock Multiplier Setting x179
528  PLLFBD_PLLFBDIV_M_180 = 0b10110100, // PLL Input Clock Multiplier Setting x180
529  PLLFBD_PLLFBDIV_M_181 = 0b10110101, // PLL Input Clock Multiplier Setting x181
530  PLLFBD_PLLFBDIV_M_182 = 0b10110110, // PLL Input Clock Multiplier Setting x182
531  PLLFBD_PLLFBDIV_M_183 = 0b10110111, // PLL Input Clock Multiplier Setting x183
532  PLLFBD_PLLFBDIV_M_184 = 0b10111000, // PLL Input Clock Multiplier Setting x184
533  PLLFBD_PLLFBDIV_M_185 = 0b10111001, // PLL Input Clock Multiplier Setting x185
534  PLLFBD_PLLFBDIV_M_186 = 0b10111010, // PLL Input Clock Multiplier Setting x186
535  PLLFBD_PLLFBDIV_M_187 = 0b10111011, // PLL Input Clock Multiplier Setting x187
536  PLLFBD_PLLFBDIV_M_188 = 0b10111100, // PLL Input Clock Multiplier Setting x188
537  PLLFBD_PLLFBDIV_M_189 = 0b10111101, // PLL Input Clock Multiplier Setting x189
538  PLLFBD_PLLFBDIV_M_190 = 0b10111110, // PLL Input Clock Multiplier Setting x190
539  PLLFBD_PLLFBDIV_M_191 = 0b10111111, // PLL Input Clock Multiplier Setting x191
540  PLLFBD_PLLFBDIV_M_192 = 0b11000000, // PLL Input Clock Multiplier Setting x192
541  PLLFBD_PLLFBDIV_M_193 = 0b11000001, // PLL Input Clock Multiplier Setting x193
542  PLLFBD_PLLFBDIV_M_194 = 0b11000010, // PLL Input Clock Multiplier Setting x194
543  PLLFBD_PLLFBDIV_M_195 = 0b11000011, // PLL Input Clock Multiplier Setting x195
544  PLLFBD_PLLFBDIV_M_196 = 0b11000100, // PLL Input Clock Multiplier Setting x196
545  PLLFBD_PLLFBDIV_M_197 = 0b11000101, // PLL Input Clock Multiplier Setting x197
546  PLLFBD_PLLFBDIV_M_198 = 0b11000110, // PLL Input Clock Multiplier Setting x198
547  PLLFBD_PLLFBDIV_M_199 = 0b11000111, // PLL Input Clock Multiplier Setting x199
548  PLLFBD_PLLFBDIV_M_200 = 0b11001000 // PLL Input Clock Multiplier Setting x200
549 } PLLFBD_PLLFBDIV_e; // PLL Feedback Divider bits (also denoted as ?M?, PLL multiplier)
550 
551 typedef struct {
552  volatile PLLFBD_PLLFBDIV_e PLLFBDIV : 8; // PLL Feedback Divider bits (also denoted as ?M?, PLL multiplier)
553  volatile unsigned : 8; // reserved
554 } PLLFBD_t;
555 
556 #else
557  #pragma message "error: === selected device family is not supported by oscillator mcal library ==="
558 #endif
559 
560 typedef union {
561  volatile uint16_t value;
562  volatile PLLFBD_t PLLFBD;
563 } REGBLK_PLLFBD_CONFIG_t;
564 
565 
566 /* ===========================================================================
567  * OSCTUN: FRC OSCILLATOR TUNING REGISTER
568  * ===========================================================================*/
569 
570 #define REG_OSCTUN_VALID_DATA_WRITE_MASK 0x003F
571 #define REG_OSCTUN_VALID_DATA_READ_MASK 0x003F
572 
573 #define REG_OSCTUN_TUNE_VALUE_MASK 0b0000000000111111
574 #define REG_OSCTUN_TUNE_VALUE(x) {(x & REG_OSCTUN_TUNE_VALUE_MASK)}
575 
576 #if defined (__P33SMPS_CH__) || defined (__P33SMPS_CK__)
577 
578 typedef enum OSCTUN_TUN_e {
579  OSCTUN_TUN_MINUS_31 = 0b100001, // Center frequency -1.457% (=7.88344 MHz)
580  OSCTUN_TUN_MINUS_30 = 0b100010, // Center frequency -1.41% (=7.8872 MHz)
581  OSCTUN_TUN_MINUS_29 = 0b100011, // Center frequency -1.363% (=7.89096 MHz)
582  OSCTUN_TUN_MINUS_28 = 0b100100, // Center frequency -1.316% (=7.89472 MHz)
583  OSCTUN_TUN_MINUS_27 = 0b100101, // Center frequency -1.269% (=7.89848 MHz)
584  OSCTUN_TUN_MINUS_26 = 0b100110, // Center frequency -1.222% (=7.90224 MHz)
585  OSCTUN_TUN_MINUS_25 = 0b100111, // Center frequency -1.175% (=7.906 MHz)
586  OSCTUN_TUN_MINUS_24 = 0b101000, // Center frequency -1.128% (=7.90976 MHz)
587  OSCTUN_TUN_MINUS_23 = 0b101001, // Center frequency -1.081% (=7.91352 MHz)
588  OSCTUN_TUN_MINUS_22 = 0b101010, // Center frequency -1.034% (=7.91728 MHz)
589  OSCTUN_TUN_MINUS_21 = 0b101011, // Center frequency -0.987% (=7.92104 MHz)
590  OSCTUN_TUN_MINUS_20 = 0b101100, // Center frequency -0.94% (=7.9248 MHz)
591  OSCTUN_TUN_MINUS_19 = 0b101101, // Center frequency -0.893% (=7.92856 MHz)
592  OSCTUN_TUN_MINUS_18 = 0b101110, // Center frequency -0.846% (=7.93232 MHz)
593  OSCTUN_TUN_MINUS_17 = 0b101111, // Center frequency -0.799% (=7.93608 MHz)
594  OSCTUN_TUN_MINUS_16 = 0b110000, // Center frequency -0.752% (=7.93984 MHz)
595  OSCTUN_TUN_MINUS_15 = 0b110001, // Center frequency -0.705% (=7.9436 MHz)
596  OSCTUN_TUN_MINUS_14 = 0b110010, // Center frequency -0.658% (=7.94736 MHz)
597  OSCTUN_TUN_MINUS_13 = 0b110011, // Center frequency -0.611% (=7.95112 MHz)
598  OSCTUN_TUN_MINUS_12 = 0b110100, // Center frequency -0.564% (=7.95488 MHz)
599  OSCTUN_TUN_MINUS_11 = 0b110101, // Center frequency -0.517% (=7.95864 MHz)
600  OSCTUN_TUN_MINUS_10 = 0b110110, // Center frequency -0.47% (=7.9624 MHz)
601  OSCTUN_TUN_MINUS_9 = 0b110111, // Center frequency -0.423% (=7.96616 MHz)
602  OSCTUN_TUN_MINUS_8 = 0b111000, // Center frequency -0.376% (=7.96992 MHz)
603  OSCTUN_TUN_MINUS_7 = 0b111001, // Center frequency -0.329% (=7.97368 MHz)
604  OSCTUN_TUN_MINUS_6 = 0b111010, // Center frequency -0.282% (=7.97744 MHz)
605  OSCTUN_TUN_MINUS_5 = 0b111011, // Center frequency -0.235% (=7.9812 MHz)
606  OSCTUN_TUN_MINUS_4 = 0b111100, // Center frequency -0.188% (=7.98496 MHz)
607  OSCTUN_TUN_MINUS_3 = 0b111101, // Center frequency -0.141% (=7.98872 MHz)
608  OSCTUN_TUN_MINUS_2 = 0b111110, // Center frequency -0.094% (=7.99248 MHz)
609  OSCTUN_TUN_MINUS_1 = 0b111111, // Center frequency -0.047% (=7.99624 MHz)
610  OSCTUN_TUN_NOMINAL = 0b000000, // Center frequency +0% (=8 MHz)
611  OSCTUN_TUN_PLUS_1 = 0b000001, // Center frequency +0.047% (=8.00376 MHz)
612  OSCTUN_TUN_PLUS_2 = 0b000010, // Center frequency +0.094% (=8.00752 MHz)
613  OSCTUN_TUN_PLUS_3 = 0b000011, // Center frequency +0.141% (=8.01128 MHz)
614  OSCTUN_TUN_PLUS_4 = 0b000100, // Center frequency +0.188% (=8.01504 MHz)
615  OSCTUN_TUN_PLUS_5 = 0b000101, // Center frequency +0.235% (=8.0188 MHz)
616  OSCTUN_TUN_PLUS_6 = 0b000110, // Center frequency +0.282% (=8.02256 MHz)
617  OSCTUN_TUN_PLUS_7 = 0b000111, // Center frequency +0.329% (=8.02632 MHz)
618  OSCTUN_TUN_PLUS_8 = 0b001000, // Center frequency +0.376% (=8.03008 MHz)
619  OSCTUN_TUN_PLUS_9 = 0b001001, // Center frequency +0.423% (=8.03384 MHz)
620  OSCTUN_TUN_PLUS_10 = 0b001010, // Center frequency +0.47% (=8.0376 MHz)
621  OSCTUN_TUN_PLUS_11 = 0b001011, // Center frequency +0.517% (=8.04136 MHz)
622  OSCTUN_TUN_PLUS_12 = 0b001100, // Center frequency +0.564% (=8.04512 MHz)
623  OSCTUN_TUN_PLUS_13 = 0b001101, // Center frequency +0.611% (=8.04888 MHz)
624  OSCTUN_TUN_PLUS_14 = 0b001110, // Center frequency +0.658% (=8.05264 MHz)
625  OSCTUN_TUN_PLUS_15 = 0b001111, // Center frequency +0.705% (=8.0564 MHz)
626  OSCTUN_TUN_PLUS_16 = 0b010000, // Center frequency +0.752% (=8.06016 MHz)
627  OSCTUN_TUN_PLUS_17 = 0b010001, // Center frequency +0.799% (=8.06392 MHz)
628  OSCTUN_TUN_PLUS_18 = 0b010010, // Center frequency +0.846% (=8.06768 MHz)
629  OSCTUN_TUN_PLUS_19 = 0b010011, // Center frequency +0.893% (=8.07144 MHz)
630  OSCTUN_TUN_PLUS_20 = 0b010100, // Center frequency +0.94% (=8.0752 MHz)
631  OSCTUN_TUN_PLUS_21 = 0b010101, // Center frequency +0.987% (=8.07896 MHz)
632  OSCTUN_TUN_PLUS_22 = 0b010110, // Center frequency +1.034% (=8.08272 MHz)
633  OSCTUN_TUN_PLUS_23 = 0b010111, // Center frequency +1.081% (=8.08648 MHz)
634  OSCTUN_TUN_PLUS_24 = 0b011000, // Center frequency +1.128% (=8.09024 MHz)
635  OSCTUN_TUN_PLUS_25 = 0b011001, // Center frequency +1.175% (=8.094 MHz)
636  OSCTUN_TUN_PLUS_26 = 0b011010, // Center frequency +1.222% (=8.09776 MHz)
637  OSCTUN_TUN_PLUS_27 = 0b011011, // Center frequency +1.269% (=8.10152 MHz)
638  OSCTUN_TUN_PLUS_28 = 0b011100, // Center frequency +1.316% (=8.10528 MHz)
639  OSCTUN_TUN_PLUS_29 = 0b011101, // Center frequency +1.363% (=8.10904 MHz)
640  OSCTUN_TUN_PLUS_30 = 0b011110, // Center frequency +1.41% (=8.1128 MHz)
641  OSCTUN_TUN_PLUS_31 = 0b011111 // Center frequency +1.457% (=8.11656 MHz)
642 } OSCTUN_TUN_t; // FRC Oscillator Tuning bits
643 
644 #else
645  #pragma message "error: === selected device family is not supported by oscillator mcal library ==="
646 #endif
647 
648 typedef struct {
649  volatile enum OSCTUN_TUN_e TUN : 6; // FRC Oscillator Tuning bits
650  volatile unsigned : 10; // reserved
651 } __attribute__((packed)) OSCTUN_t;
652 
653 typedef union {
654  volatile uint16_t value;
655  volatile OSCTUN_t OSCTUN;
656 } REGBLK_OSCTUN_CONFIG_t;
657 
658 
659 /* ===========================================================================
660  * PLLDIV: PLL OUTPUT DIVIDER REGISTER
661  * ===========================================================================*/
662 
663 #if defined (__P33SMPS_CH__) || defined (__P33SMPS_CK__)
664 
665 #define REG_PLLDIV_VALID_DATA_WRITE_MASK 0x0377
666 #define REG_PLLDIV_VALID_DATA_READ_MASK 0x0377
667 
668 #define REG_PLLDIV_POST1DIV_N2_MASK 0b0000000001110000
669 #define REG_PLLDIV_POST1DIV_N2(x) {((x << 4) & REG_PLLDIV_POST1DIV_N2_MASK)}
670 
671 #define REG_PLLDIV_POST2DIV_N3_MASK 0b0000000000000111
672 #define REG_PLLDIV_POST2DIV_N3(x) {(x & REG_PLLDIV_POST1DIV_N3_MASK)}
673 
674 typedef enum {
675  PLLDIV_POST2DIV_N2N3_1 = 0b001, // PLL Output Divider Ratio bits 1:1
676  PLLDIV_POST2DIV_N2N3_2 = 0b010, // PLL Output Divider Ratio bits 1:2
677  PLLDIV_POST2DIV_N2N3_3 = 0b011, // PLL Output Divider Ratio bits 1:3
678  PLLDIV_POST2DIV_N2N3_4 = 0b100, // PLL Output Divider Ratio bits 1:4
679  PLLDIV_POST2DIV_N2N3_5 = 0b101, // PLL Output Divider Ratio bits 1:5
680  PLLDIV_POST2DIV_N2N3_6 = 0b110, // PLL Output Divider Ratio bits 1:6
681  PLLDIV_POST2DIV_N2N3_7 = 0b111 // PLL Output Divider Ratio bits 1:7
682 } PLLDIV_POSTxDIV_e; // PLL Output Divider Ratio bits (also denoted as ?N2? and ?N3?, PLL divider)
683 
684 #define REG_PLLDIV_VCODIV_FVCO_DIV_BY_1 0b0000001100000000
685 #define REG_PLLDIV_VCODIV_FVCO_DIV_BY_2 0b0000001000000000
686 #define REG_PLLDIV_VCODIV_FVCO_DIV_BY_3 0b0000000100000000
687 #define REG_PLLDIV_VCODIV_FVCO_DIV_BY_4 0b0000000000000000
688 
689 typedef enum {
690  PLLDIV_VCODIV_FVCO_DIV_BY_1 = 0b11, // PLL VCO Output Divider 1:1
691  PLLDIV_VCODIV_FVCO_DIV_BY_2 = 0b10, // PLL VCO Output Divider 1:2
692  PLLDIV_VCODIV_FVCO_DIV_BY_3 = 0b01, // PLL VCO Output Divider 1:3
693  PLLDIV_VCODIV_FVCO_DIV_BY_4 = 0b00 // PLL VCO Output Divider 1:4
694 } PLLDIV_VCODIV_e; // PLL VCO Output Divider Select bits
695 
696 typedef struct {
697  volatile PLLDIV_POSTxDIV_e POST2DIV : 3;
698  volatile unsigned : 1;
699  volatile PLLDIV_POSTxDIV_e POST1DIV : 3;
700  volatile unsigned : 1;
701  volatile PLLDIV_VCODIV_e VCODIV : 2;
702  volatile unsigned : 6;
703 } __attribute__((packed)) PLLDIV_t;
704 
705 typedef union {
706  volatile uint16_t value;
707  volatile PLLDIV_t PLLDIV;
708 } REGBLK_PLLDIV_CONFIG_t;
709 
710 #endif
711 
712 
713 /* ===========================================================================
714  * ACLKCON1: AUXILIARY CLOCK CONTROL REGISTER
715  * ===========================================================================*/
716 
717 #if defined (__P33SMPS_CH__) || defined (__P33SMPS_CK__)
718 
719 #define REG_ACLKCON_VALID_DATA_WRITE_MASK 0xC10F
720 #define REG_ACLKCON_VALID_DATA_READ_MASK 0xC10F
721 
722 #define REG_ACLKCON_APLLPRE_DIV_MASK 0b0000000000001111
723 #define REG_ACLKCON_APLLPRE_DIVIDER_N1(x) {(x & REG_ACLKCON_APLLPRE_DIV_MASK)}
724 
725 typedef enum {
726  ACLKCON_APLLDIV_N1_1 = 0b000001, // APLL Input Clock Divider Setting 1:1
727  ACLKCON_APLLDIV_N1_2 = 0b000010, // APLL Input Clock Divider Setting 1:2
728  ACLKCON_APLLDIV_N1_3 = 0b000011, // APLL Input Clock Divider Setting 1:3
729  ACLKCON_APLLDIV_N1_4 = 0b000100, // APLL Input Clock Divider Setting 1:4
730  ACLKCON_APLLDIV_N1_5 = 0b000101, // APLL Input Clock Divider Setting 1:5
731  ACLKCON_APLLDIV_N1_6 = 0b000110, // APLL Input Clock Divider Setting 1:6
732  ACLKCON_APLLDIV_N1_7 = 0b000111, // APLL Input Clock Divider Setting 1:7
733  ACLKCON_APLLDIV_N1_8 = 0b001000 // APLL Input Clock Divider Setting 1:8
734 } ACLKCON_APLLPRE_e; // PLL Phase Detector Input Divider Select bits (also denoted as ?N1?, PLL prescaler)
735 
736 #define REG_ACLKCON_FRCSEL_FRC 0b0000000100000000
737 #define REG_ACLKCON_FRCSEL_PRI 0b0000000000000000
738 
739 typedef enum {
740  PLLDIV_ACLKCON_FRCSEL_FRC = 0b1, // FRC is the clock source for APLL
741  PLLDIV_ACLKCON_FRCSEL_PRI = 0b0 // Primary Oscillator is the clock source for APLL
742 } ACLKCON_FRCSEL_e; // APLL Clock Source Select bit
743 
744 #define REG_ACLKCON_APLLCK_STAT_LOCKED 0b0100000000000000
745 #define REG_ACLKCON_APLLCK_STAT_UNLOCKED 0b0000000000000000
746 
747 typedef enum {
748  ACLKCON_APLLCK_STAT_LOCKED = 0b1, // APLL Phase-Locked State Status bit
749  ACLKCON_APLLCK_STAT_UNLOCKED = 0b0 // Auxiliary PLL is not in lock
750 } ACLKCON_APLLCK_e; // APLL Phase-Locked State Status bit
751 
752 #define REG_ACLKCON_APLLEN_ENABLED 0b1000000000000000
753 #define REG_ACLKCON_APLLEN_DISABLED 0b0000000000000000
754 
755 typedef enum {
756  ACLKCON_APLLEN_ENABLED = 0b1, // AFPLLO is connected to the APLL post-divider output (bypass disabled)
757  ACLKCON_APLLEN_DISABLED = 0b0 // AFPLLO is connected to the APLL input clock (bypass enabled)
758 } ACLKCON_APLLEN_e; // Auxiliary PLL Enable/Bypass select bit
759 
760 typedef struct {
761  volatile ACLKCON_APLLPRE_e APLLPRE : 6;
762  volatile unsigned : 2;
763  volatile ACLKCON_FRCSEL_e FRCSEL : 1;
764  volatile unsigned : 5;
765  volatile ACLKCON_APLLCK_e APLLCK : 1;
766  volatile ACLKCON_APLLEN_e APLLEN : 1;
767 } ACLKCON_t;
768 
769 typedef union {
770  volatile uint16_t value;
771  volatile ACLKCON_t ACLKCON; // APLL Feedback Divider bits
772 } REGBLK_ACLKCON_CONFIG_t;
773 
774 #else
775  #pragma message "error: === selected device family is not supported by oscillator mcal library ==="
776 #endif
777 
778 /* ===========================================================================
779  * APLLFBD1: APLL FEEDBACK DIVIDER REGISTER
780  * ===========================================================================*/
781 
782 #if defined (__P33SMPS_CH__) || defined (__P33SMPS_CK__)
783 
784 #define REG_APLLFBD_VALID_DATA_WRITE_MASK 0x00FF
785 #define REG_APLLFBD_VALID_DATA_READ_MASK 0x00FF
786 
787 #define REG_APLLFBD_APLLFBDIV_M_MASK 0b0000000011111111
788 #define REG_APLLFBD_MULTIPLIER_M(x) {(x & REG_APLLFBD_APLLFBDIV_M_MASK)}
789 
790 typedef enum {
791  APLLFBD_APLLFBDIV_M_16 = 0b00010000, // APLL Input Clock Multiplier Setting x16
792  APLLFBD_APLLFBDIV_M_17 = 0b00010001, // APLL Input Clock Multiplier Setting x17
793  APLLFBD_APLLFBDIV_M_18 = 0b00010010, // APLL Input Clock Multiplier Setting x18
794  APLLFBD_APLLFBDIV_M_19 = 0b00010011, // APLL Input Clock Multiplier Setting x19
795  APLLFBD_APLLFBDIV_M_20 = 0b00010100, // APLL Input Clock Multiplier Setting x20
796  APLLFBD_APLLFBDIV_M_21 = 0b00010101, // APLL Input Clock Multiplier Setting x21
797  APLLFBD_APLLFBDIV_M_22 = 0b00010110, // APLL Input Clock Multiplier Setting x22
798  APLLFBD_APLLFBDIV_M_23 = 0b00010111, // APLL Input Clock Multiplier Setting x23
799  APLLFBD_APLLFBDIV_M_24 = 0b00011000, // APLL Input Clock Multiplier Setting x24
800  APLLFBD_APLLFBDIV_M_25 = 0b00011001, // APLL Input Clock Multiplier Setting x25
801  APLLFBD_APLLFBDIV_M_26 = 0b00011010, // APLL Input Clock Multiplier Setting x26
802  APLLFBD_APLLFBDIV_M_27 = 0b00011011, // APLL Input Clock Multiplier Setting x27
803  APLLFBD_APLLFBDIV_M_28 = 0b00011100, // APLL Input Clock Multiplier Setting x28
804  APLLFBD_APLLFBDIV_M_29 = 0b00011101, // APLL Input Clock Multiplier Setting x29
805  APLLFBD_APLLFBDIV_M_30 = 0b00011110, // APLL Input Clock Multiplier Setting x30
806  APLLFBD_APLLFBDIV_M_31 = 0b00011111, // APLL Input Clock Multiplier Setting x31
807  APLLFBD_APLLFBDIV_M_32 = 0b00100000, // APLL Input Clock Multiplier Setting x32
808  APLLFBD_APLLFBDIV_M_33 = 0b00100001, // APLL Input Clock Multiplier Setting x33
809  APLLFBD_APLLFBDIV_M_34 = 0b00100010, // APLL Input Clock Multiplier Setting x34
810  APLLFBD_APLLFBDIV_M_35 = 0b00100011, // APLL Input Clock Multiplier Setting x35
811  APLLFBD_APLLFBDIV_M_36 = 0b00100100, // APLL Input Clock Multiplier Setting x36
812  APLLFBD_APLLFBDIV_M_37 = 0b00100101, // APLL Input Clock Multiplier Setting x37
813  APLLFBD_APLLFBDIV_M_38 = 0b00100110, // APLL Input Clock Multiplier Setting x38
814  APLLFBD_APLLFBDIV_M_39 = 0b00100111, // APLL Input Clock Multiplier Setting x39
815  APLLFBD_APLLFBDIV_M_40 = 0b00101000, // APLL Input Clock Multiplier Setting x40
816  APLLFBD_APLLFBDIV_M_41 = 0b00101001, // APLL Input Clock Multiplier Setting x41
817  APLLFBD_APLLFBDIV_M_42 = 0b00101010, // APLL Input Clock Multiplier Setting x42
818  APLLFBD_APLLFBDIV_M_43 = 0b00101011, // APLL Input Clock Multiplier Setting x43
819  APLLFBD_APLLFBDIV_M_44 = 0b00101100, // APLL Input Clock Multiplier Setting x44
820  APLLFBD_APLLFBDIV_M_45 = 0b00101101, // APLL Input Clock Multiplier Setting x45
821  APLLFBD_APLLFBDIV_M_46 = 0b00101110, // APLL Input Clock Multiplier Setting x46
822  APLLFBD_APLLFBDIV_M_47 = 0b00101111, // APLL Input Clock Multiplier Setting x47
823  APLLFBD_APLLFBDIV_M_48 = 0b00110000, // APLL Input Clock Multiplier Setting x48
824  APLLFBD_APLLFBDIV_M_49 = 0b00110001, // APLL Input Clock Multiplier Setting x49
825  APLLFBD_APLLFBDIV_M_50 = 0b00110010, // APLL Input Clock Multiplier Setting x50
826  APLLFBD_APLLFBDIV_M_51 = 0b00110011, // APLL Input Clock Multiplier Setting x51
827  APLLFBD_APLLFBDIV_M_52 = 0b00110100, // APLL Input Clock Multiplier Setting x52
828  APLLFBD_APLLFBDIV_M_53 = 0b00110101, // APLL Input Clock Multiplier Setting x53
829  APLLFBD_APLLFBDIV_M_54 = 0b00110110, // APLL Input Clock Multiplier Setting x54
830  APLLFBD_APLLFBDIV_M_55 = 0b00110111, // APLL Input Clock Multiplier Setting x55
831  APLLFBD_APLLFBDIV_M_56 = 0b00111000, // APLL Input Clock Multiplier Setting x56
832  APLLFBD_APLLFBDIV_M_57 = 0b00111001, // APLL Input Clock Multiplier Setting x57
833  APLLFBD_APLLFBDIV_M_58 = 0b00111010, // APLL Input Clock Multiplier Setting x58
834  APLLFBD_APLLFBDIV_M_59 = 0b00111011, // APLL Input Clock Multiplier Setting x59
835  APLLFBD_APLLFBDIV_M_60 = 0b00111100, // APLL Input Clock Multiplier Setting x60
836  APLLFBD_APLLFBDIV_M_61 = 0b00111101, // APLL Input Clock Multiplier Setting x61
837  APLLFBD_APLLFBDIV_M_62 = 0b00111110, // APLL Input Clock Multiplier Setting x62
838  APLLFBD_APLLFBDIV_M_63 = 0b00111111, // APLL Input Clock Multiplier Setting x63
839  APLLFBD_APLLFBDIV_M_64 = 0b01000000, // APLL Input Clock Multiplier Setting x64
840  APLLFBD_APLLFBDIV_M_65 = 0b01000001, // APLL Input Clock Multiplier Setting x65
841  APLLFBD_APLLFBDIV_M_66 = 0b01000010, // APLL Input Clock Multiplier Setting x66
842  APLLFBD_APLLFBDIV_M_67 = 0b01000011, // APLL Input Clock Multiplier Setting x67
843  APLLFBD_APLLFBDIV_M_68 = 0b01000100, // APLL Input Clock Multiplier Setting x68
844  APLLFBD_APLLFBDIV_M_69 = 0b01000101, // APLL Input Clock Multiplier Setting x69
845  APLLFBD_APLLFBDIV_M_70 = 0b01000110, // APLL Input Clock Multiplier Setting x70
846  APLLFBD_APLLFBDIV_M_71 = 0b01000111, // APLL Input Clock Multiplier Setting x71
847  APLLFBD_APLLFBDIV_M_72 = 0b01001000, // APLL Input Clock Multiplier Setting x72
848  APLLFBD_APLLFBDIV_M_73 = 0b01001001, // APLL Input Clock Multiplier Setting x73
849  APLLFBD_APLLFBDIV_M_74 = 0b01001010, // APLL Input Clock Multiplier Setting x74
850  APLLFBD_APLLFBDIV_M_75 = 0b01001011, // APLL Input Clock Multiplier Setting x75
851  APLLFBD_APLLFBDIV_M_76 = 0b01001100, // APLL Input Clock Multiplier Setting x76
852  APLLFBD_APLLFBDIV_M_77 = 0b01001101, // APLL Input Clock Multiplier Setting x77
853  APLLFBD_APLLFBDIV_M_78 = 0b01001110, // APLL Input Clock Multiplier Setting x78
854  APLLFBD_APLLFBDIV_M_79 = 0b01001111, // APLL Input Clock Multiplier Setting x79
855  APLLFBD_APLLFBDIV_M_80 = 0b01010000, // APLL Input Clock Multiplier Setting x80
856  APLLFBD_APLLFBDIV_M_81 = 0b01010001, // APLL Input Clock Multiplier Setting x81
857  APLLFBD_APLLFBDIV_M_82 = 0b01010010, // APLL Input Clock Multiplier Setting x82
858  APLLFBD_APLLFBDIV_M_83 = 0b01010011, // APLL Input Clock Multiplier Setting x83
859  APLLFBD_APLLFBDIV_M_84 = 0b01010100, // APLL Input Clock Multiplier Setting x84
860  APLLFBD_APLLFBDIV_M_85 = 0b01010101, // APLL Input Clock Multiplier Setting x85
861  APLLFBD_APLLFBDIV_M_86 = 0b01010110, // APLL Input Clock Multiplier Setting x86
862  APLLFBD_APLLFBDIV_M_87 = 0b01010111, // APLL Input Clock Multiplier Setting x87
863  APLLFBD_APLLFBDIV_M_88 = 0b01011000, // APLL Input Clock Multiplier Setting x88
864  APLLFBD_APLLFBDIV_M_89 = 0b01011001, // APLL Input Clock Multiplier Setting x89
865  APLLFBD_APLLFBDIV_M_90 = 0b01011010, // APLL Input Clock Multiplier Setting x90
866  APLLFBD_APLLFBDIV_M_91 = 0b01011011, // APLL Input Clock Multiplier Setting x91
867  APLLFBD_APLLFBDIV_M_92 = 0b01011100, // APLL Input Clock Multiplier Setting x92
868  APLLFBD_APLLFBDIV_M_93 = 0b01011101, // APLL Input Clock Multiplier Setting x93
869  APLLFBD_APLLFBDIV_M_94 = 0b01011110, // APLL Input Clock Multiplier Setting x94
870  APLLFBD_APLLFBDIV_M_95 = 0b01011111, // APLL Input Clock Multiplier Setting x95
871  APLLFBD_APLLFBDIV_M_96 = 0b01100000, // APLL Input Clock Multiplier Setting x96
872  APLLFBD_APLLFBDIV_M_97 = 0b01100001, // APLL Input Clock Multiplier Setting x97
873  APLLFBD_APLLFBDIV_M_98 = 0b01100010, // APLL Input Clock Multiplier Setting x98
874  APLLFBD_APLLFBDIV_M_99 = 0b01100011, // APLL Input Clock Multiplier Setting x99
875  APLLFBD_APLLFBDIV_M_100 = 0b01100100, // APLL Input Clock Multiplier Setting x100
876  APLLFBD_APLLFBDIV_M_101 = 0b01100101, // APLL Input Clock Multiplier Setting x101
877  APLLFBD_APLLFBDIV_M_102 = 0b01100110, // APLL Input Clock Multiplier Setting x102
878  APLLFBD_APLLFBDIV_M_103 = 0b01100111, // APLL Input Clock Multiplier Setting x103
879  APLLFBD_APLLFBDIV_M_104 = 0b01101000, // APLL Input Clock Multiplier Setting x104
880  APLLFBD_APLLFBDIV_M_105 = 0b01101001, // APLL Input Clock Multiplier Setting x105
881  APLLFBD_APLLFBDIV_M_106 = 0b01101010, // APLL Input Clock Multiplier Setting x106
882  APLLFBD_APLLFBDIV_M_107 = 0b01101011, // APLL Input Clock Multiplier Setting x107
883  APLLFBD_APLLFBDIV_M_108 = 0b01101100, // APLL Input Clock Multiplier Setting x108
884  APLLFBD_APLLFBDIV_M_109 = 0b01101101, // APLL Input Clock Multiplier Setting x109
885  APLLFBD_APLLFBDIV_M_110 = 0b01101110, // APLL Input Clock Multiplier Setting x110
886  APLLFBD_APLLFBDIV_M_111 = 0b01101111, // APLL Input Clock Multiplier Setting x111
887  APLLFBD_APLLFBDIV_M_112 = 0b01110000, // APLL Input Clock Multiplier Setting x112
888  APLLFBD_APLLFBDIV_M_113 = 0b01110001, // APLL Input Clock Multiplier Setting x113
889  APLLFBD_APLLFBDIV_M_114 = 0b01110010, // APLL Input Clock Multiplier Setting x114
890  APLLFBD_APLLFBDIV_M_115 = 0b01110011, // APLL Input Clock Multiplier Setting x115
891  APLLFBD_APLLFBDIV_M_116 = 0b01110100, // APLL Input Clock Multiplier Setting x116
892  APLLFBD_APLLFBDIV_M_117 = 0b01110101, // APLL Input Clock Multiplier Setting x117
893  APLLFBD_APLLFBDIV_M_118 = 0b01110110, // APLL Input Clock Multiplier Setting x118
894  APLLFBD_APLLFBDIV_M_119 = 0b01110111, // APLL Input Clock Multiplier Setting x119
895  APLLFBD_APLLFBDIV_M_120 = 0b01111000, // APLL Input Clock Multiplier Setting x120
896  APLLFBD_APLLFBDIV_M_121 = 0b01111001, // APLL Input Clock Multiplier Setting x121
897  APLLFBD_APLLFBDIV_M_122 = 0b01111010, // APLL Input Clock Multiplier Setting x122
898  APLLFBD_APLLFBDIV_M_123 = 0b01111011, // APLL Input Clock Multiplier Setting x123
899  APLLFBD_APLLFBDIV_M_124 = 0b01111100, // APLL Input Clock Multiplier Setting x124
900  APLLFBD_APLLFBDIV_M_125 = 0b01111101, // APLL Input Clock Multiplier Setting x125
901  APLLFBD_APLLFBDIV_M_126 = 0b01111110, // APLL Input Clock Multiplier Setting x126
902  APLLFBD_APLLFBDIV_M_127 = 0b01111111, // APLL Input Clock Multiplier Setting x127
903  APLLFBD_APLLFBDIV_M_128 = 0b10000000, // APLL Input Clock Multiplier Setting x128
904  APLLFBD_APLLFBDIV_M_129 = 0b10000001, // APLL Input Clock Multiplier Setting x129
905  APLLFBD_APLLFBDIV_M_130 = 0b10000010, // APLL Input Clock Multiplier Setting x130
906  APLLFBD_APLLFBDIV_M_131 = 0b10000011, // APLL Input Clock Multiplier Setting x131
907  APLLFBD_APLLFBDIV_M_132 = 0b10000100, // APLL Input Clock Multiplier Setting x132
908  APLLFBD_APLLFBDIV_M_133 = 0b10000101, // APLL Input Clock Multiplier Setting x133
909  APLLFBD_APLLFBDIV_M_134 = 0b10000110, // APLL Input Clock Multiplier Setting x134
910  APLLFBD_APLLFBDIV_M_135 = 0b10000111, // APLL Input Clock Multiplier Setting x135
911  APLLFBD_APLLFBDIV_M_136 = 0b10001000, // APLL Input Clock Multiplier Setting x136
912  APLLFBD_APLLFBDIV_M_137 = 0b10001001, // APLL Input Clock Multiplier Setting x137
913  APLLFBD_APLLFBDIV_M_138 = 0b10001010, // APLL Input Clock Multiplier Setting x138
914  APLLFBD_APLLFBDIV_M_139 = 0b10001011, // APLL Input Clock Multiplier Setting x139
915  APLLFBD_APLLFBDIV_M_140 = 0b10001100, // APLL Input Clock Multiplier Setting x140
916  APLLFBD_APLLFBDIV_M_141 = 0b10001101, // APLL Input Clock Multiplier Setting x141
917  APLLFBD_APLLFBDIV_M_142 = 0b10001110, // APLL Input Clock Multiplier Setting x142
918  APLLFBD_APLLFBDIV_M_143 = 0b10001111, // APLL Input Clock Multiplier Setting x143
919  APLLFBD_APLLFBDIV_M_144 = 0b10010000, // APLL Input Clock Multiplier Setting x144
920  APLLFBD_APLLFBDIV_M_145 = 0b10010001, // APLL Input Clock Multiplier Setting x145
921  APLLFBD_APLLFBDIV_M_146 = 0b10010010, // APLL Input Clock Multiplier Setting x146
922  APLLFBD_APLLFBDIV_M_147 = 0b10010011, // APLL Input Clock Multiplier Setting x147
923  APLLFBD_APLLFBDIV_M_148 = 0b10010100, // APLL Input Clock Multiplier Setting x148
924  APLLFBD_APLLFBDIV_M_149 = 0b10010101, // APLL Input Clock Multiplier Setting x149
925  APLLFBD_APLLFBDIV_M_150 = 0b10010110, // APLL Input Clock Multiplier Setting x150
926  APLLFBD_APLLFBDIV_M_151 = 0b10010111, // APLL Input Clock Multiplier Setting x151
927  APLLFBD_APLLFBDIV_M_152 = 0b10011000, // APLL Input Clock Multiplier Setting x152
928  APLLFBD_APLLFBDIV_M_153 = 0b10011001, // APLL Input Clock Multiplier Setting x153
929  APLLFBD_APLLFBDIV_M_154 = 0b10011010, // APLL Input Clock Multiplier Setting x154
930  APLLFBD_APLLFBDIV_M_155 = 0b10011011, // APLL Input Clock Multiplier Setting x155
931  APLLFBD_APLLFBDIV_M_156 = 0b10011100, // APLL Input Clock Multiplier Setting x156
932  APLLFBD_APLLFBDIV_M_157 = 0b10011101, // APLL Input Clock Multiplier Setting x157
933  APLLFBD_APLLFBDIV_M_158 = 0b10011110, // APLL Input Clock Multiplier Setting x158
934  APLLFBD_APLLFBDIV_M_159 = 0b10011111, // APLL Input Clock Multiplier Setting x159
935  APLLFBD_APLLFBDIV_M_160 = 0b10100000, // APLL Input Clock Multiplier Setting x160
936  APLLFBD_APLLFBDIV_M_161 = 0b10100001, // APLL Input Clock Multiplier Setting x161
937  APLLFBD_APLLFBDIV_M_162 = 0b10100010, // APLL Input Clock Multiplier Setting x162
938  APLLFBD_APLLFBDIV_M_163 = 0b10100011, // APLL Input Clock Multiplier Setting x163
939  APLLFBD_APLLFBDIV_M_164 = 0b10100100, // APLL Input Clock Multiplier Setting x164
940  APLLFBD_APLLFBDIV_M_165 = 0b10100101, // APLL Input Clock Multiplier Setting x165
941  APLLFBD_APLLFBDIV_M_166 = 0b10100110, // APLL Input Clock Multiplier Setting x166
942  APLLFBD_APLLFBDIV_M_167 = 0b10100111, // APLL Input Clock Multiplier Setting x167
943  APLLFBD_APLLFBDIV_M_168 = 0b10101000, // APLL Input Clock Multiplier Setting x168
944  APLLFBD_APLLFBDIV_M_169 = 0b10101001, // APLL Input Clock Multiplier Setting x169
945  APLLFBD_APLLFBDIV_M_170 = 0b10101010, // APLL Input Clock Multiplier Setting x170
946  APLLFBD_APLLFBDIV_M_171 = 0b10101011, // APLL Input Clock Multiplier Setting x171
947  APLLFBD_APLLFBDIV_M_172 = 0b10101100, // APLL Input Clock Multiplier Setting x172
948  APLLFBD_APLLFBDIV_M_173 = 0b10101101, // APLL Input Clock Multiplier Setting x173
949  APLLFBD_APLLFBDIV_M_174 = 0b10101110, // APLL Input Clock Multiplier Setting x174
950  APLLFBD_APLLFBDIV_M_175 = 0b10101111, // APLL Input Clock Multiplier Setting x175
951  APLLFBD_APLLFBDIV_M_176 = 0b10110000, // APLL Input Clock Multiplier Setting x176
952  APLLFBD_APLLFBDIV_M_177 = 0b10110001, // APLL Input Clock Multiplier Setting x177
953  APLLFBD_APLLFBDIV_M_178 = 0b10110010, // APLL Input Clock Multiplier Setting x178
954  APLLFBD_APLLFBDIV_M_179 = 0b10110011, // APLL Input Clock Multiplier Setting x179
955  APLLFBD_APLLFBDIV_M_180 = 0b10110100, // APLL Input Clock Multiplier Setting x180
956  APLLFBD_APLLFBDIV_M_181 = 0b10110101, // APLL Input Clock Multiplier Setting x181
957  APLLFBD_APLLFBDIV_M_182 = 0b10110110, // APLL Input Clock Multiplier Setting x182
958  APLLFBD_APLLFBDIV_M_183 = 0b10110111, // APLL Input Clock Multiplier Setting x183
959  APLLFBD_APLLFBDIV_M_184 = 0b10111000, // APLL Input Clock Multiplier Setting x184
960  APLLFBD_APLLFBDIV_M_185 = 0b10111001, // APLL Input Clock Multiplier Setting x185
961  APLLFBD_APLLFBDIV_M_186 = 0b10111010, // APLL Input Clock Multiplier Setting x186
962  APLLFBD_APLLFBDIV_M_187 = 0b10111011, // APLL Input Clock Multiplier Setting x187
963  APLLFBD_APLLFBDIV_M_188 = 0b10111100, // APLL Input Clock Multiplier Setting x188
964  APLLFBD_APLLFBDIV_M_189 = 0b10111101, // APLL Input Clock Multiplier Setting x189
965  APLLFBD_APLLFBDIV_M_190 = 0b10111110, // APLL Input Clock Multiplier Setting x190
966  APLLFBD_APLLFBDIV_M_191 = 0b10111111, // APLL Input Clock Multiplier Setting x191
967  APLLFBD_APLLFBDIV_M_192 = 0b11000000, // APLL Input Clock Multiplier Setting x192
968  APLLFBD_APLLFBDIV_M_193 = 0b11000001, // APLL Input Clock Multiplier Setting x193
969  APLLFBD_APLLFBDIV_M_194 = 0b11000010, // APLL Input Clock Multiplier Setting x194
970  APLLFBD_APLLFBDIV_M_195 = 0b11000011, // APLL Input Clock Multiplier Setting x195
971  APLLFBD_APLLFBDIV_M_196 = 0b11000100, // APLL Input Clock Multiplier Setting x196
972  APLLFBD_APLLFBDIV_M_197 = 0b11000101, // APLL Input Clock Multiplier Setting x197
973  APLLFBD_APLLFBDIV_M_198 = 0b11000110, // APLL Input Clock Multiplier Setting x198
974  APLLFBD_APLLFBDIV_M_199 = 0b11000111, // APLL Input Clock Multiplier Setting x199
975  APLLFBD_APLLFBDIV_M_200 = 0b11001000 // APLL Input Clock Multiplier Setting x200
976 } APLLFBD_APLLFBDIV_e; // APLL Feedback Divider bits (also denoted as ?M?, PLL multiplier)
977 
978 typedef struct {
979  volatile APLLFBD_APLLFBDIV_e APLLFBDIV : 8; // APLL Feedback Divider bits (also denoted as ?M?, PLL multiplier)
980  volatile unsigned : 8; // reserved
981 } APLLFBD_t; // APLL Feedback Divider bits
982 
983 typedef union {
984  volatile uint16_t value;
985  volatile APLLFBD_t APLLFBD; // APLL Feedback Divider bits
986 } REGBLK_APLLFBD_CONFIG_t;
987 
988 #else
989  #pragma message "error: === selected device family is not supported by oscillator mcal library ==="
990 #endif
991 
992 /* ===========================================================================
993  * APLLDIV1: APLL OUTPUT DIVIDER REGISTER
994  * ===========================================================================*/
995 
996 #if defined (__P33SMPS_CH__) || defined (__P33SMPS_CK__)
997 
998 #define REG_APLLDIV_VALID_DATA_WRITE_MASK 0x0377
999 #define REG_APLLDIV_VALID_DATA_READ_MASK 0x0377
1000 
1001 #define REG_APLLDIV_POST1DIV_N2_MASK 0b0000000001110000
1002 #define REG_APLLDIV_POST1DIV_N2(x) {((x << 4) & REG_APLLDIV_POST1DIV_N2_MASK)}
1003 
1004 #define REG_APLLDIV_POST2DIV_N3_MASK 0b0000000000000111
1005 #define REG_APLLDIV_POST2DIV_N3(x) {(x & REG_APLLDIV_POST1DIV_N3_MASK)}
1006 
1007 typedef enum {
1008  APLLDIV_POST2DIV_N2N3_1 = 0b001, // PLL Output Divider Ratio bits 1:1
1009  APLLDIV_POST2DIV_N2N3_2 = 0b010, // PLL Output Divider Ratio bits 1:2
1010  APLLDIV_POST2DIV_N2N3_3 = 0b011, // PLL Output Divider Ratio bits 1:3
1011  APLLDIV_POST2DIV_N2N3_4 = 0b100, // PLL Output Divider Ratio bits 1:4
1012  APLLDIV_POST2DIV_N2N3_5 = 0b101, // PLL Output Divider Ratio bits 1:5
1013  APLLDIV_POST2DIV_N2N3_6 = 0b110, // PLL Output Divider Ratio bits 1:6
1014  APLLDIV_POST2DIV_N2N3_7 = 0b111 // PLL Output Divider Ratio bits 1:7
1015 } APLLDIV_POSTxDIV_e; // PLL Output Divider Ratio bits (also denoted as ?N2? and ?N3?, PLL divider)
1016 
1017 #define REG_APLLDIV_AVCODIV_FVCO_DIV_BY_1 0b0000001100000000
1018 #define REG_APLLDIV_AVCODIV_FVCO_DIV_BY_2 0b0000001000000000
1019 #define REG_APLLDIV_AVCODIV_FVCO_DIV_BY_3 0b0000000100000000
1020 #define REG_APLLDIV_AVCODIV_FVCO_DIV_BY_4 0b0000000000000000
1021 
1022 typedef enum {
1023  APLLDIV_AVCODIV_FVCO_DIV_BY_1 = 0b11, // APLL AVCO Output Divider 1:1
1024  APLLDIV_AVCODIV_FVCO_DIV_BY_2 = 0b10, // APLL AVCO Output Divider 1:2
1025  APLLDIV_AVCODIV_FVCO_DIV_BY_3 = 0b01, // APLL AVCO Output Divider 1:3
1026  APLLDIV_AVCODIV_FVCO_DIV_BY_4 = 0b00 // APLL AVCO Output Divider 1:4
1027 } APLLDIV_AVCODIV_e; // APLL AVCO Output Divider Select bits
1028 
1029 typedef struct {
1030  volatile APLLDIV_POSTxDIV_e APOST2DIV : 3;
1031  volatile unsigned : 1;
1032  volatile APLLDIV_POSTxDIV_e APOST1DIV : 3;
1033  volatile unsigned : 1;
1034  volatile APLLDIV_AVCODIV_e AVCODIV : 2;
1035  volatile unsigned : 6;
1036 } __attribute__((packed)) APLLDIV_t;
1037 
1038 typedef union {
1039  volatile uint16_t value;
1040  volatile APLLDIV_t APLLDIV; // APLL Output Divider Select bits
1041 } REGBLK_APLLDIV_CONFIG_t;
1042 
1043 #else
1044  #pragma message "error: === selected device family is not supported by oscillator mcal library ==="
1045 #endif
1046 
1047 /* ===========================================================================
1048  * OSCILLATOR CONFIGURATION OBJECT
1049  * ===========================================================================*/
1050 
1051 #if defined (__P33SMPS_CH__) || defined (__P33SMPS_CK__)
1052 
1053 typedef struct OSC_CONFIG_s {
1054  volatile OSCCON_xOSC_TYPE_e osc_type;
1055  volatile enum CLKDIV_FRCDIVN_e frc_div;
1056  volatile enum OSCTUN_TUN_e frc_tune;
1057  volatile CLKDIV_PLLPRE_e N1;
1058  volatile PLLFBD_PLLFBDIV_e M;
1059  volatile PLLDIV_POSTxDIV_e N2;
1060  volatile PLLDIV_POSTxDIV_e N3;
1061  volatile PLLDIV_VCODIV_e VCODIV;
1062 } OSC_CONFIG_t;
1063 
1064 typedef struct AUXOSC_CONFIG_s {
1065  volatile ACLKCON_APLLPRE_e N1;
1066  volatile APLLFBD_APLLFBDIV_e M;
1067  volatile APLLDIV_POSTxDIV_e N2;
1068  volatile APLLDIV_POSTxDIV_e N3;
1069  volatile APLLDIV_AVCODIV_e AVCODIV;
1070  volatile ACLKCON_FRCSEL_e FRCSEL : 1;
1071  volatile ACLKCON_APLLCK_e APLLCK : 1;
1072  volatile ACLKCON_APLLEN_e APLLEN : 1;
1073 } AUXOSC_CONFIG_t;
1074 
1075 #else
1076  #pragma message "error: === selected device family is not supported by oscillator mcal library ==="
1077 #endif
1078 
1079 
1080 /* ***************************************************************************************
1081  * ERROR CODES
1082  * **************************************************************************************/
1083 
1084 typedef enum OSC_CFG_ERR_RESULT_e{
1085  OSCERR_FAILURE = 0x0000, // Global Clock Error
1086  OSCERR_SUCCESS = 0x0001, // Clock initialization was successfully performed
1087  OSCERR_CSF = 0x0002, // Clock switch-over failed
1088  OSCERR_RST = 0x0004, // Clock switch-over failed
1089  OSCERR_CSD = 0x0008, // Clock switching is disabled but desired clock differs from current clock
1090  OSCERR_PLL_LCK = 0x0010, // Primary PLL does not lock in
1091  OSCERR_APLL_LCK = 0x0020, // Auxiliary PLL does not lock in
1092 } OSC_CFG_ERR_RESULT_t;
1093 
1094 
1095 /* ***************************************************************************************
1096  * Prototypes
1097  * **************************************************************************************/
1098 
1099 extern volatile uint16_t p33c_Osc_Initialize(volatile struct OSC_CONFIG_s osc_config);
1100 extern volatile uint16_t p33c_OscFrc_Initialize(volatile enum CLKDIV_FRCDIVN_e frc_div, volatile enum OSCTUN_TUN_e frc_tun);
1101 extern volatile uint16_t p33c_OscAuxClk_Initialize(volatile struct AUXOSC_CONFIG_s aux_clock_config);
1102 
1103 extern volatile uint16_t p33c_OscFrc_DefaultInitialize(volatile enum CPU_SPEED_DEFAULTS_e cpu_speed);
1104 extern volatile uint16_t p33c_OscAuxClk_DefaultInitialize(volatile enum AUX_PLL_DEFAULTS_e afpllo_frequency);
1105 extern volatile uint16_t p33c_Osc_GetFrequencies(volatile uint32_t main_osc_frequency);
1106 
1107 #endif /* MCAL_P33SMPS_OSCILLATOR_H */
p33c_OscAuxClk_Initialize
volatile uint16_t p33c_OscAuxClk_Initialize(volatile struct AUXOSC_CONFIG_s aux_clock_config)
Initializes the auxiliary clock and its PLL module step by step in software. Each step is tested and ...
Definition: p33c_osc.c:301
p33c_OscFrc_DefaultInitialize
volatile uint16_t p33c_OscFrc_DefaultInitialize(volatile enum CPU_SPEED_DEFAULTS_e cpu_speed)
Initializes the major oscillator and the PLL module step by step by using clock switching in software...
Definition: p33c_osc.c:62
p33c_OscFrc_Initialize
volatile uint16_t p33c_OscFrc_Initialize(volatile enum CLKDIV_FRCDIVN_e frc_div, volatile enum OSCTUN_TUN_e frc_tun)
Initializes the internal RC oscillator divider and tuning register.
Definition: p33c_osc.c:138
p33c_Osc_GetFrequencies
volatile uint16_t p33c_Osc_GetFrequencies(volatile uint32_t main_osc_frequency)
This routine reads all oscillator related SFRs recalculating the various frequencies across clock dom...
Definition: p33c_osc.c:418
p33c_OscAuxClk_DefaultInitialize
volatile uint16_t p33c_OscAuxClk_DefaultInitialize(volatile enum AUX_PLL_DEFAULTS_e afpllo_frequency)
Initializes the auxiliary clock and its PLL module step by step in software. Each step is tested and ...
Definition: p33c_osc.c:352
OSCILLATOR_SYSTEM_FREQUENCIES_s
Global data structure holding system frequencies of different clock domains.
Definition: p33c_osc.h:125
OSCILLATOR_SYSTEM_FREQUENCIES_s::afvco
volatile uint32_t afvco
Definition: p33c_osc.h:137
OSCILLATOR_SYSTEM_FREQUENCIES_s::fclk
volatile uint32_t fclk
Definition: p33c_osc.h:128
OSCILLATOR_SYSTEM_FREQUENCIES_s::fvco
volatile uint32_t fvco
Definition: p33c_osc.h:133
OSCILLATOR_SYSTEM_FREQUENCIES_s::fosc
volatile uint32_t fosc
Definition: p33c_osc.h:129
OSCILLATOR_SYSTEM_FREQUENCIES_s::fpri
volatile uint32_t fpri
Definition: p33c_osc.h:127
OSCILLATOR_SYSTEM_FREQUENCIES_s::afpllo
volatile uint32_t afpllo
Definition: p33c_osc.h:136
OSCILLATOR_SYSTEM_FREQUENCIES_s::fpllo
volatile uint32_t fpllo
Definition: p33c_osc.h:132
OSCCON_t::CF
volatile OSCCON_CF_e CF
Definition: p33c_osc.h:237
OSCCON_t::unsigned
volatile unsigned
Definition: p33c_osc.h:236
OSCCON_t::CLKLOCK
volatile OSCCON_CLKLOCK_e CLKLOCK
Definition: p33c_osc.h:241
OSCCON_t::LOCK
volatile OSCCON_LOCK_e LOCK
Definition: p33c_osc.h:239
OSCCON_t::OSWEN
volatile OSCCON_OSWEN_e OSWEN
Definition: p33c_osc.h:235
OSCCON_t::COSC
volatile OSCCON_xOSC_TYPE_e COSC
Definition: p33c_osc.h:244
OSCCON_t::NOSC
volatile OSCCON_xOSC_TYPE_e NOSC
Definition: p33c_osc.h:242
REGBLK_OSCCON_CONFIG_t::value
volatile uint16_t value
Definition: p33c_osc.h:249
REGBLK_OSCCON_CONFIG_t::OSCCON
volatile OSCCON_t OSCCON
Definition: p33c_osc.h:250
CLKDIV_t::ROI
volatile CLKDIV_ROI_e ROI
Definition: p33c_osc.h:342
CLKDIV_t::PLLPRE
volatile CLKDIV_PLLPRE_e PLLPRE
Definition: p33c_osc.h:337
CLKDIV_t::DOZEN
volatile CLKDIV_DOZEN_e DOZEN
Definition: p33c_osc.h:340
CLKDIV_t::DOZE
volatile CLKDIV_DOZE_e DOZE
Definition: p33c_osc.h:341
REGBLK_CLKDIV_CONFIG_t::value
volatile uint16_t value
Definition: p33c_osc.h:346
REGBLK_CLKDIV_CONFIG_t::CLKDIV
volatile CLKDIV_t CLKDIV
Definition: p33c_osc.h:347
REGBLK_PLLFBD_CONFIG_t::PLLFBD
volatile PLLFBD_t PLLFBD
Definition: p33c_osc.h:562
REGBLK_PLLFBD_CONFIG_t::value
volatile uint16_t value
Definition: p33c_osc.h:561
OSCTUN_t::unsigned
volatile unsigned
Definition: p33c_osc.h:650
REGBLK_OSCTUN_CONFIG_t::value
volatile uint16_t value
Definition: p33c_osc.h:654
REGBLK_OSCTUN_CONFIG_t::OSCTUN
volatile OSCTUN_t OSCTUN
Definition: p33c_osc.h:655