35 #ifndef P33C_DMA_SFR_ABSTRACTION_H 36 #define P33C_DMA_SFR_ABSTRACTION_H 46 #ifndef P33C_DMA_MODULE_s 62 volatile struct tagDMACONBITS
bits;
83 } __attribute__((packed));
99 #define p33c_DmaModule_GetHandle() (struct P33C_DMA_MODULE_s*)&DMACON 101 #endif // end of P33C_DMA_MODULE_s 104 #ifndef P33C_DMA_INSTANCE_s 120 volatile struct tagDMACH0BITS
bits;
124 volatile struct tagDMAINT0BITS
bits;
125 volatile uint16_t
value;
145 } __attribute__((packed));
158 #define P33C_DMA_COUNT 8 159 #elif defined (DMACH6) 160 #define P33C_DMA_COUNT 7 161 #elif defined (DMACH5) 162 #define P33C_DMA_COUNT 6 163 #elif defined (DMACH4) 164 #define P33C_DMA_COUNT 5 165 #elif defined (DMACH3) 166 #define P33C_DMA_COUNT 4 167 #elif defined (DMACH2) 168 #define P33C_DMA_COUNT 3 169 #elif defined (DMACH1) 170 #define P33C_DMA_COUNT 2 172 #pragma message "selected device has no supported DMA channels" 184 #ifndef P33C_DMA_SFR_OFFSET 185 #define P33C_DMA_SFR_OFFSET ((volatile uint16_t)&DMACH1 - (volatile uint16_t)&DMACH0) 198 #define P33C_DACL_DEFAULT 0x0000 // Default DMA address range minimum address 210 #define P33C_DACH_DEFAULT 0x4FFF // Default DMA address range maximum address 226 extern volatile uint16_t* p33c_DmaChannel_Handles[];
227 #define p33c_DmaInstance_GetHandle(x) (struct P33C_DMA_INSTANCE_s*)p33c_DmaChannel_Handles[(x)] 230 #endif // end of P33C_DMA_INSTANCE_s 232 #define DMATRG_INT0 0x00 // External Interrupt 0 233 #define DMATRG_SCCP1 0x01 // SCCP1 Interrupt 234 #define DMATRG_SPI1_RX 0x02 // SPI1 Receiver 235 #define DMATRG_SPI1_TX 0x03 // SPI1 Transmitter 236 #define DMATRG_UART1_RX 0x04 // UART1 Receiver 237 #define DMATRG_UART1_TX 0x05 // UART1 Transmitter 238 #define DMATRG_ECC_BERR 0x06 // ECC Single Bit Error 239 #define DMATRG_NVM_WRITE 0x07 // NVM Write Complete 240 #define DMATRG_INT1 0x08 // External Interrupt 1 241 #define DMATRG_SI2C1 0x09 // I2C1 Device Event 242 #define DMATRG_MI2C1 0x0A // I2C1 Host Event 243 #define DMATRG_INT2 0x0B // External Interrupt 2 244 #define DMATRG_SCCP2 0x0C // SCCP2 Interrupt 245 #define DMATRG_INT3 0x0D // External Interrupt 3 246 #define DMATRG_UART2_RX 0x0E // UART2 Receiver 247 #define DMATRG_UART2_TX 0x0F // UART2 Transmitter 248 #define DMATRG_SPI2_RX 0x10 // SPI2 Receiver 249 #define DMATRG_SPI2_TX 0x11 // SPI2 Transmitter 250 #define DMATRG_SCCP3 0x12 // SCCP3 Interrupt 251 #define DMATRG_SI2C2 0x13 // I2C2 Device Event 252 #define DMATRG_MI2C2 0x14 // I2C2 Host Event 253 #define DMATRG_SCCP4 0x15 // SCCP4 Interrupt 254 #define DMATRG_SCCP5 0x16 // SCCP5 Interrupt 255 #define DMATRG_SCCP6 0x17 // SCCP6 Interrupt 256 #define DMATRG_CRC 0x18 // CRC Generator Interrupt 257 #define DMATRG_PWM_EVTA 0x19 // PWM Event A 258 #define DMATRG_PWM_EVTB 0x1B // PWM Event B 259 #define DMATRG_PG1EVT 0x1C // PWM Generator 1 260 #define DMATRG_PG2EVT 0x1D // PWM Generator 2 261 #define DMATRG_PG3EVT 0x1E // PWM Generator 3 262 #define DMATRG_PG4EVT 0x1F // PWM Generator 4 263 #define DMATRG_PG5EVT 0x20 // PWM Generator 5 264 #define DMATRG_PG6EVT 0x21 // PWM Generator 6 265 #define DMATRG_PG7EVT 0x22 // PWM Generator 7 266 #define DMATRG_PG8EVT 0x23 // PWM Generator 8 267 #define DMATRG_PWM_EVTC 0x24 // PWM Event C 268 #define DMATRG_SENT1 0x25 // SENT1 TX/RX 269 #define DMATRG_SENT2 0x26 // SENT2 TX/RX 270 #define DMATRG_ADC_DONE 0x27 // ADC1 Group Convert Done 271 #define DMATRG_AN0_DONE 0x28 // ADC Done AN0 272 #define DMATRG_AN1_DONE 0x29 // ADC Done AN1 273 #define DMATRG_AN2_DONE 0x2A // ADC Done AN2 274 #define DMATRG_AN3_DONE 0x2B // ADC Done AN3 275 #define DMATRG_AN4_DONE 0x2C // ADC Done AN4 276 #define DMATRG_AN5_DONE 0x2D // ADC Done AN5 277 #define DMATRG_AN6_DONE 0x2E // ADC Done AN6 278 #define DMATRG_AN7_DONE 0x2F // ADC Done AN7 279 #define DMATRG_AN8_DONE 0x30 // ADC Done AN8 280 #define DMATRG_AN9_DONE 0x31 // ADC Done AN9 281 #define DMATRG_AN10_DONE 0x32 // ADC Done AN10 282 #define DMATRG_AN11_DONE 0x33 // ADC Done AN11 283 #define DMATRG_AN12_DONE 0x34 // ADC Done AN12 284 #define DMATRG_AN13_DONE 0x35 // ADC Done AN13 285 #define DMATRG_AN14_DONE 0x36 // ADC Done AN14 286 #define DMATRG_AN15_DONE 0x37 // ADC Done AN15 287 #define DMATRG_AN16_DONE 0x38 // ADC Done AN16 288 #define DMATRG_AN17_DONE 0x39 // ADC Done AN17 289 #define DMATRG_AN18_DONE 0x3A // ADC Done AN18 290 #define DMATRG_AN19_DONE 0x3B // ADC Done AN19 291 #define DMATRG_AN20_DONE 0x3C // ADC Done AN20 292 #define DMATRG_AN21_DONE 0x3D // ADC Done AN21 293 #define DMATRG_AN22_DONE 0x3E // ADC Done AN22 294 #define DMATRG_AN23_DONE 0x3F // ADC Done AN23 295 #define DMATRG_AD1FLTR1 0x40 // Oversample Filter 1 296 #define DMATRG_AD1FLTR2 0x41 // Oversample Filter 2 297 #define DMATRG_AD1FLTR3 0x42 // Oversample Filter 3 298 #define DMATRG_AD1FLTR4 0x43 // Oversample Filter 4 299 #define DMATRG_CLC1 0x44 // CPC1 Positive Edge Interrupt 300 #define DMATRG_CLC2 0x45 // CPC2 Positive Edge Interrupt 301 #define DMATRG_SPI1_FLT 0x46 // SPI1 Fault Interrupt 302 #define DMATRG_SPI2_FLT 0x47 // SPI2 Fault Interrupt 303 #define DMATRG_PWM_EVTD 0x57 // PWM Event D 304 #define DMATRG_PWM_EVTE 0x58 // PWM Event E 305 #define DMATRG_PWM_EVTF 0x59 // PWM Event F 306 #define DMATRG_SCCP7 0x5C // SCCP7 Interrupt 307 #define DMATRG_SCCP8 0x5D // SCCP8 Interrupt 308 #define DMATRG_CLC3 0x60 // CPC1 Positive Edge Interrupt 309 #define DMATRG_CLC4 0x61 // CPC2 Positive Edge Interrupt 310 #define DMATRG_SPI3_RX 0x62 // SPI3 Receiver 311 #define DMATRG_SPI3_TX 0x63 // SPI3 Transmitter 312 #define DMATRG_SI2C3 0x64 // I2C3 Device Event 313 #define DMATRG_MI2C3 0x65 // I2C3 Host Event 314 #define DMATRG_SPI3_FLT 0x66 // SPI3 Fault Interrupt 315 #define DMATRG_MCCP9 0x67 // MCCP9 Interrupt 316 #define DMATRG_UART3_RX 0x68 // UART3 Receiver 317 #define DMATRG_UART3_TX 0x69 // UART3 Transmitter 318 #define DMATRG_AN24_DONE 0x6A // ADC Done AN24 319 #define DMATRG_AN25_DONE 0x6B // ADC Done AN25 320 #define DMATRG_PMP_EVT 0x6C // PMP Event 321 #define DMATRG_PMP_ERR 0x6D // PMP Error Event 328 extern volatile uint16_t p33c_DmaModule_Dispose(
void);
330 extern volatile uint16_t p33c_DmaModule_ConfigWrite(
335 extern volatile uint16_t p33c_DmaInstance_Dispose(
volatile uint16_t dmaInstance);
336 extern volatile struct P33C_DMA_INSTANCE_s p33c_DmaInstance_ConfigRead(volatile uint16_t dmaInstance);
337 extern volatile uint16_t p33c_DmaInstance_ConfigWrite(
338 volatile uint16_t dmaInstance,
union P33C_DMA_INSTANCE_s::@106 DMACHx
union P33C_DMA_MODULE_s::@93 DmaBuf
union P33C_DMA_INSTANCE_s::@107 DMAINTx
union P33C_DMA_MODULE_s::@92 DmaCon
volatile struct tagDMACH0BITS bits
union P33C_DMA_INSTANCE_s::@108 DMASRCx
union P33C_DMA_INSTANCE_s::@110 DMACNTx
volatile struct tagDMACONBITS bits
union P33C_DMA_INSTANCE_s::@109 DMADSTx
union P33C_DMA_MODULE_s::@94 DmaL
union P33C_DMA_MODULE_s::@95 DmaH