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pwm.c
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1
17/*
18© [2025] Microchip Technology Inc. and its subsidiaries.
19
20 Subject to your compliance with these terms, you may use Microchip
21 software and any derivatives exclusively with Microchip products.
22 You are responsible for complying with 3rd party license terms
23 applicable to your use of 3rd party software (including open source
24 software) that may accompany Microchip software. SOFTWARE IS ?AS IS.?
25 NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS
26 SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT,
27 MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT
28 WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
29 INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY
30 KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
31 MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE
32 FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP?S
33 TOTAL LIABILITY ON ALL CLAIMS RELATED TO THE SOFTWARE WILL NOT
34 EXCEED AMOUNT OF FEES, IF ANY, YOU PAID DIRECTLY TO MICROCHIP FOR
35 THIS SOFTWARE.
36*/
37
38// Section: Included Files
39
40
41#include "../pwm.h"
42
43// Section: File specific functions
44
45static void (*PWM_GeneratorEOCEventHandler)(enum PWM_GENERATOR genNum) = NULL;
46
47
48// Section: Driver Interface
49
50const struct PWM_HS_INTERFACE PWM_HS = {
51 .Initialize = &PWM_Initialize,
52 .Deinitialize = &PWM_Deinitialize,
53 .Disable = &PWM_Disable,
54 .Enable = &PWM_Enable,
55 .ModeSet = &PWM_ModeSet,
56 .MasterPeriodSet = &PWM_MasterPeriodSet,
57 .MasterDutyCycleSet = &PWM_MasterDutyCycleSet,
58 .PeriodSet = &PWM_PeriodSet,
59 .DutyCycleSet = &PWM_DutyCycleSet,
60 .PhaseSelect = &PWM_PhaseSelect,
61 .PhaseSet = &PWM_PhaseSet,
62 .OverrideDataSet = &PWM_OverrideDataSet,
63 .OverrideDataHighSet = &PWM_OverrideDataHighSet,
64 .OverrideDataLowSet = &PWM_OverrideDataLowSet,
65 .OverrideDataGet = &PWM_OverrideDataGet,
66 .OverrideHighEnable = &PWM_OverrideHighEnable,
67 .OverrideLowEnable = &PWM_OverrideLowEnable,
68 .OverrideHighDisable = &PWM_OverrideHighDisable,
69 .OverrideLowDisable = &PWM_OverrideLowDisable,
70 .DeadTimeLowSet = &PWM_DeadTimeLowSet,
71 .DeadTimeHighSet = &PWM_DeadTimeHighSet,
72 .DeadTimeSet = &PWM_DeadTimeSet,
73 .TriggerCompareValueSet = &PWM_TriggerCompareValueSet,
74 .GeneratorInterruptEnable = &PWM_GeneratorInterruptEnable,
75 .GeneratorInterruptDisable = &PWM_GeneratorInterruptDisable,
76 .GeneratorEventStatusGet = &PWM_GeneratorEventStatusGet,
77 .GeneratorEventStatusClear = &PWM_GeneratorEventStatusClear,
78
79 .SpecialEventPrimaryCompareValueSet = NULL,
80 .SpecialEventTriggerInterruptFlagClear = NULL,
81 .SpecialEventPrimaryInterruptEnable = NULL,
82 .SpecialEventPrimaryInterruptDisable = NULL,
83 .FaultModeLatchDisable = NULL,
84 .FaultModeLatchEnable = NULL,
85 .MasterPhaseSet = &PWM_MasterPhaseSet,
86 .GeneratorDisable = &PWM_GeneratorDisable,
87 .GeneratorEnable = &PWM_GeneratorEnable,
88 .TriggerACompareValueSet = &PWM_TriggerACompareValueSet,
89 .TriggerBCompareValueSet = &PWM_TriggerBCompareValueSet,
90 .TriggerCCompareValueSet = &PWM_TriggerCCompareValueSet,
91 .SoftwareUpdateRequest = &PWM_SoftwareUpdateRequest,
92 .SoftwareUpdatePending = &PWM_SoftwareUpdatePending,
93 .FaultModeLatchClear = &PWM_FaultModeLatchClear,
94 .Trigger1Enable = &PWM_Trigger1Enable,
95 .Trigger1Disable = &PWM_Trigger1Disable,
96 .Trigger2Enable = &PWM_Trigger2Enable,
97 .Trigger2Disable = &PWM_Trigger2Disable,
98
99 .GeneratorEOCEventCallbackRegister = &PWM_GeneratorEOCEventCallbackRegister,
100
101
102 .GeneratorTasks = &PWM_GeneratorTasks,
103 .CommonEventTasks = NULL,
104};
105
106// Section: PWM Module APIs
107
108void PWM_Initialize (void)
109{
110 // MODSEL Independent Edge; TRGCNT 1; CLKSEL Master clock; ON disabled; HREN enabled;
111 PG1CONL = 0x88;
112 // MODSEL Independent Edge; TRGCNT 1; CLKSEL Master clock; ON disabled; HREN enabled;
113 PG2CONL = 0x88;
114 // MODSEL Independent Edge; TRGCNT 1; CLKSEL Master clock; ON disabled; HREN enabled;
115 PG3CONL = 0x88;
116 // MODSEL Independent Edge; TRGCNT 1; CLKSEL Master clock; ON disabled; HREN enabled;
117 PG4CONL = 0x88;
118 //
119 PG1CAP = 0x0;
120 // PCIGT disabled; TQPS Not inverted; SWPCI Drives '0'; BPEN disabled; TQSS None; SWPCIM PCI acceptance logic; BPSEL PWM Generator 1; ACP Level-sensitive;
121 PG1CLPCIH = 0x0;
122 // PSS Tied to 0; PPS Not inverted; SWTERM disabled; PSYNC disabled; TERM Manual Terminate; AQPS Not inverted; AQSS None; TSYNCDIS PWM EOC;
123 PG1CLPCIL = 0x0;
124 // MSTEN disabled; TRIGMOD Single trigger mode; SOCS Self-trigger; UPDMOD SOC update; MPHSEL disabled; MPERSEL disabled; MDCSEL disabled;
125 PG1CONH = 0x0;
126 // DC1 20000;
127 PG1DC = 0x4E20;
128 // DCA1 0x0;
129 PG1DCA = 0x0;
130 // DTH1 600;
131 PG1DTH = 0x258;
132 // DTL1 600;
133 PG1DTL = 0x258;
134 // ADTR2EN1 disabled; IEVTSEL EOC; SIEN disabled; FFIEN disabled; ADTR1OFS None; CLIEN disabled; FLTIEN disabled; ADTR2EN2 enabled; ADTR2EN3 disabled;
135 PG1EVTH = 0x40;
136 // UPDTRG Trigger A; ADTR1PS 1:1; PGTRGSEL Trigger A compare event; ADTR1EN3 disabled; ADTR1EN1 enabled; ADTR1EN2 disabled;
137 PG1EVTL = 0x119;
138 // PCIGT disabled; TQPS Not inverted; SWPCI Drives '0'; BPEN disabled; TQSS None; SWPCIM PCI acceptance logic; BPSEL PWM Generator 1; ACP Level-sensitive;
139 PG1FFPCIH = 0x0;
140 // PSS Tied to 0; PPS Not inverted; SWTERM disabled; PSYNC disabled; TERM Manual Terminate; AQPS Not inverted; AQSS None; TSYNCDIS PWM EOC;
141 PG1FFPCIL = 0x0;
142 // TQPS Not inverted; LATMOD disabled; SWPCI Drives '0'; BPEN disabled; TQSS None; SWPCIM PCI acceptance logic; BPSEL PWM Generator 1; ACP Level-sensitive;
143 PG1FPCIH = 0x0;
144 // PSS Tied to 0; PPS Not inverted; SWTERM disabled; PSYNC disabled; TERM Manual Terminate; AQPS Not inverted; AQSS None; TSYNCDIS PWM EOC;
145 PG1FPCIL = 0x0;
146 // PENL enabled; DTCMPSEL PCI Sync Logic; PMOD Complementary; POLL Active-high; PENH enabled; CAPSRC Software; POLH Active-high;
147 PG1IOCONH = 0xC;
148 // FLTDAT 0; DBDAT 0x0; SWAP disabled; OVRENH disabled; OVRENL disabled; OSYNC User output overrides occur when specified by UPDMOD bits; CLMOD disabled; FFDAT 0x0; CLDAT 0x0; OVRDAT 0;
149 PG1IOCONL = 0x200;
150 // PWMPCI PWM1; PLR disabled; PLF disabled; PHR disabled; PHF disabled;
151 PG1LEBH = 0x0;
152 // LEB 0x0;
153 PG1LEBL = 0x0;
154 // PER1 39992;
155 PG1PER = 0x9C38;
156 // PHASE1 0;
157 PG1PHASE = 0x0;
158 // PCIGT disabled; TQPS Not inverted; SWPCI Drives '0'; BPEN disabled; TQSS None; SWPCIM PCI acceptance logic; BPSEL PWM Generator 1; ACP Level-sensitive;
159 PG1SPCIH = 0x0;
160 // PSS Tied to 0; PPS Not inverted; SWTERM disabled; PSYNC disabled; TERM Manual Terminate; AQPS Not inverted; AQSS None; TSYNCDIS PWM EOC;
161 PG1SPCIL = 0x0;
162 // TRSET disabled; UPDREQ disabled; CLEVT disabled; TRCLR disabled; CAP disabled; SEVT disabled; FFEVT disabled; UPDATE disabled; FLTEVT disabled;
163 PG1STAT = 0x0;
164 // TRIGA1 0;
165 PG1TRIGA = 0x0;
166 // TRIGB1 0;
167 PG1TRIGB = 0x0;
168 // TRIGC1 0;
169 PG1TRIGC = 0x0;
170 //
171 PG2CAP = 0x0;
172 // PCIGT disabled; TQPS Not inverted; SWPCI Drives '0'; BPEN disabled; TQSS None; SWPCIM PCI acceptance logic; BPSEL PWM Generator 1; ACP Level-sensitive;
173 PG2CLPCIH = 0x0;
174 // PSS Tied to 0; PPS Not inverted; SWTERM disabled; PSYNC disabled; TERM Manual Terminate; AQPS Not inverted; AQSS None; TSYNCDIS PWM EOC;
175 PG2CLPCIL = 0x0;
176 // MSTEN disabled; TRIGMOD Single trigger mode; SOCS Trigger output selected by PG3 or PG7; UPDMOD SOC update; MPHSEL disabled; MPERSEL disabled; MDCSEL disabled;
177 PG2CONH = 0x3;
178 // DC2 0;
179 PG2DC = 0x0;
180 // DCA2 0x0;
181 PG2DCA = 0x0;
182 // DTH2 600;
183 PG2DTH = 0x258;
184 // DTL2 600;
185 PG2DTL = 0x258;
186 // ADTR2EN1 disabled; IEVTSEL EOC; SIEN disabled; FFIEN disabled; ADTR1OFS None; CLIEN disabled; FLTIEN disabled; ADTR2EN2 disabled; ADTR2EN3 disabled;
187 PG2EVTH = 0x0;
188 // UPDTRG Duty Cycle; ADTR1PS 1:1; PGTRGSEL EOC event; ADTR1EN3 disabled; ADTR1EN1 disabled; ADTR1EN2 disabled;
189 PG2EVTL = 0x8;
190 // PCIGT disabled; TQPS Not inverted; SWPCI Drives '0'; BPEN disabled; TQSS None; SWPCIM PCI acceptance logic; BPSEL PWM Generator 1; ACP Level-sensitive;
191 PG2FFPCIH = 0x0;
192 // PSS Tied to 0; PPS Not inverted; SWTERM disabled; PSYNC disabled; TERM Manual Terminate; AQPS Not inverted; AQSS None; TSYNCDIS PWM EOC;
193 PG2FFPCIL = 0x0;
194 // TQPS Not inverted; LATMOD disabled; SWPCI Drives '0'; BPEN disabled; TQSS None; SWPCIM PCI acceptance logic; BPSEL PWM Generator 1; ACP Level-sensitive;
195 PG2FPCIH = 0x0;
196 // PSS Tied to 0; PPS Not inverted; SWTERM disabled; PSYNC disabled; TERM Manual Terminate; AQPS Not inverted; AQSS None; TSYNCDIS PWM EOC;
197 PG2FPCIL = 0x0;
198 // PENL enabled; DTCMPSEL PCI Sync Logic; PMOD Complementary; POLL Active-high; PENH enabled; CAPSRC Software; POLH Active-high;
199 PG2IOCONH = 0xC;
200 // FLTDAT 0; DBDAT 0x0; SWAP disabled; OVRENH enabled; OVRENL disabled; OSYNC User output overrides occur when specified by UPDMOD bits; CLMOD disabled; FFDAT 0x0; CLDAT 0x0; OVRDAT 0;
201 PG2IOCONL = 0x2200;
202 // PWMPCI PWM1; PLR disabled; PLF disabled; PHR disabled; PHF disabled;
203 PG2LEBH = 0x0;
204 // LEB 0x0;
205 PG2LEBL = 0x0;
206 // PER2 39992;
207 PG2PER = 0x9C38;
208 // PHASE2 0;
209 PG2PHASE = 0x0;
210 // PCIGT disabled; TQPS Not inverted; SWPCI Drives '0'; BPEN disabled; TQSS None; SWPCIM PCI acceptance logic; BPSEL PWM Generator 1; ACP Level-sensitive;
211 PG2SPCIH = 0x0;
212 // PSS Tied to 0; PPS Not inverted; SWTERM disabled; PSYNC disabled; TERM Manual Terminate; AQPS Not inverted; AQSS None; TSYNCDIS PWM EOC;
213 PG2SPCIL = 0x0;
214 // TRSET disabled; UPDREQ disabled; CLEVT disabled; TRCLR disabled; CAP disabled; SEVT disabled; FFEVT disabled; UPDATE disabled; FLTEVT disabled;
215 PG2STAT = 0x0;
216 // TRIGA2 0;
217 PG2TRIGA = 0x0;
218 // TRIGB2 0;
219 PG2TRIGB = 0x0;
220 // TRIGC2 0;
221 PG2TRIGC = 0x0;
222 //
223 PG3CAP = 0x0;
224 // PCIGT disabled; TQPS Not inverted; SWPCI Drives '0'; BPEN disabled; TQSS None; SWPCIM PCI acceptance logic; BPSEL PWM Generator 1; ACP Level-sensitive;
225 PG3CLPCIH = 0x0;
226 // PSS Tied to 0; PPS Not inverted; SWTERM disabled; PSYNC disabled; TERM Manual Terminate; AQPS Not inverted; AQSS None; TSYNCDIS PWM EOC;
227 PG3CLPCIL = 0x0;
228 // MSTEN disabled; TRIGMOD Single trigger mode; SOCS Trigger output selected by PG1 or PG5; UPDMOD SOC update; MPHSEL disabled; MPERSEL disabled; MDCSEL disabled;
229 PG3CONH = 0x1;
230 // DC3 20000;
231 PG3DC = 0x4E20;
232 // DCA3 0x0;
233 PG3DCA = 0x0;
234 // DTH3 600;
235 PG3DTH = 0x258;
236 // DTL3 600;
237 PG3DTL = 0x258;
238 // ADTR2EN1 disabled; IEVTSEL EOC; SIEN disabled; FFIEN disabled; ADTR1OFS None; CLIEN disabled; FLTIEN disabled; ADTR2EN2 disabled; ADTR2EN3 disabled;
239 PG3EVTH = 0x0;
240 // UPDTRG Trigger A; ADTR1PS 1:1; PGTRGSEL Trigger A compare event; ADTR1EN3 disabled; ADTR1EN1 disabled; ADTR1EN2 disabled;
241 PG3EVTL = 0x19;
242 // PCIGT disabled; TQPS Not inverted; SWPCI Drives '0'; BPEN disabled; TQSS None; SWPCIM PCI acceptance logic; BPSEL PWM Generator 1; ACP Level-sensitive;
243 PG3FFPCIH = 0x0;
244 // PSS Tied to 0; PPS Not inverted; SWTERM disabled; PSYNC disabled; TERM Manual Terminate; AQPS Not inverted; AQSS None; TSYNCDIS PWM EOC;
245 PG3FFPCIL = 0x0;
246 // TQPS Not inverted; LATMOD disabled; SWPCI Drives '0'; BPEN disabled; TQSS None; SWPCIM PCI acceptance logic; BPSEL PWM Generator 1; ACP Level-sensitive;
247 PG3FPCIH = 0x0;
248 // PSS Tied to 0; PPS Not inverted; SWTERM disabled; PSYNC disabled; TERM Manual Terminate; AQPS Not inverted; AQSS None; TSYNCDIS PWM EOC;
249 PG3FPCIL = 0x0;
250 // PENL enabled; DTCMPSEL PCI Sync Logic; PMOD Complementary; POLL Active-high; PENH enabled; CAPSRC Software; POLH Active-high;
251 PG3IOCONH = 0xC;
252 // FLTDAT 0; DBDAT 0x0; SWAP disabled; OVRENH disabled; OVRENL disabled; OSYNC User output overrides occur when specified by UPDMOD bits; CLMOD disabled; FFDAT 0x0; CLDAT 0x0; OVRDAT 0;
253 PG3IOCONL = 0x200;
254 // PWMPCI PWM1; PLR disabled; PLF disabled; PHR disabled; PHF disabled;
255 PG3LEBH = 0x0;
256 // LEB 0x0;
257 PG3LEBL = 0x0;
258 // PER3 39992;
259 PG3PER = 0x9C38;
260 // PHASE3 0;
261 PG3PHASE = 0x0;
262 // PCIGT disabled; TQPS Not inverted; SWPCI Drives '0'; BPEN disabled; TQSS None; SWPCIM PCI acceptance logic; BPSEL PWM Generator 1; ACP Level-sensitive;
263 PG3SPCIH = 0x0;
264 // PSS Tied to 0; PPS Not inverted; SWTERM disabled; PSYNC disabled; TERM Manual Terminate; AQPS Not inverted; AQSS None; TSYNCDIS PWM EOC;
265 PG3SPCIL = 0x0;
266 // TRSET disabled; UPDREQ disabled; CLEVT disabled; TRCLR disabled; CAP disabled; SEVT disabled; FFEVT disabled; UPDATE disabled; FLTEVT disabled;
267 PG3STAT = 0x0;
268 // TRIGA3 0;
269 PG3TRIGA = 0x0;
270 // TRIGB3 0;
271 PG3TRIGB = 0x0;
272 // TRIGC3 0;
273 PG3TRIGC = 0x0;
274 //
275 PG4CAP = 0x0;
276 // PCIGT disabled; TQPS Not inverted; SWPCI Drives '0'; BPEN disabled; TQSS None; SWPCIM PCI acceptance logic; BPSEL PWM Generator 1; ACP Level-sensitive;
277 PG4CLPCIH = 0x0;
278 // PSS Tied to 0; PPS Not inverted; SWTERM disabled; PSYNC disabled; TERM Manual Terminate; AQPS Not inverted; AQSS None; TSYNCDIS PWM EOC;
279 PG4CLPCIL = 0x0;
280 // MSTEN disabled; TRIGMOD Single trigger mode; SOCS Trigger output selected by PG1 or PG5; UPDMOD SOC update; MPHSEL disabled; MPERSEL disabled; MDCSEL disabled;
281 PG4CONH = 0x1;
282 // DC4 0;
283 PG4DC = 0x0;
284 // DCA4 0x0;
285 PG4DCA = 0x0;
286 // DTH4 600;
287 PG4DTH = 0x258;
288 // DTL4 600;
289 PG4DTL = 0x258;
290 // ADTR2EN1 disabled; IEVTSEL EOC; SIEN disabled; FFIEN disabled; ADTR1OFS None; CLIEN disabled; FLTIEN disabled; ADTR2EN2 disabled; ADTR2EN3 disabled;
291 PG4EVTH = 0x0;
292 // UPDTRG Trigger A; ADTR1PS 1:1; PGTRGSEL EOC event; ADTR1EN3 disabled; ADTR1EN1 disabled; ADTR1EN2 disabled;
293 PG4EVTL = 0x18;
294 // PCIGT disabled; TQPS Not inverted; SWPCI Drives '0'; BPEN disabled; TQSS None; SWPCIM PCI acceptance logic; BPSEL PWM Generator 1; ACP Level-sensitive;
295 PG4FFPCIH = 0x0;
296 // PSS Tied to 0; PPS Not inverted; SWTERM disabled; PSYNC disabled; TERM Manual Terminate; AQPS Not inverted; AQSS None; TSYNCDIS PWM EOC;
297 PG4FFPCIL = 0x0;
298 // TQPS Not inverted; LATMOD disabled; SWPCI Drives '0'; BPEN disabled; TQSS None; SWPCIM PCI acceptance logic; BPSEL PWM Generator 1; ACP Level-sensitive;
299 PG4FPCIH = 0x0;
300 // PSS Tied to 0; PPS Not inverted; SWTERM disabled; PSYNC disabled; TERM Manual Terminate; AQPS Not inverted; AQSS None; TSYNCDIS PWM EOC;
301 PG4FPCIL = 0x0;
302 // PENL enabled; DTCMPSEL PCI Sync Logic; PMOD Complementary; POLL Active-high; PENH enabled; CAPSRC Software; POLH Active-high;
303 PG4IOCONH = 0xC;
304 // FLTDAT 0; DBDAT 0x0; SWAP disabled; OVRENH enabled; OVRENL disabled; OSYNC User output overrides occur when specified by UPDMOD bits; CLMOD disabled; FFDAT 0x0; CLDAT 0x0; OVRDAT 0;
305 PG4IOCONL = 0x2200;
306 // PWMPCI PWM1; PLR disabled; PLF disabled; PHR disabled; PHF disabled;
307 PG4LEBH = 0x0;
308 // LEB 0x0;
309 PG4LEBL = 0x0;
310 // PER4 39992;
311 PG4PER = 0x9C38;
312 // PHASE4 0;
313 PG4PHASE = 0x0;
314 // PCIGT disabled; TQPS Not inverted; SWPCI Drives '0'; BPEN disabled; TQSS None; SWPCIM PCI acceptance logic; BPSEL PWM Generator 1; ACP Level-sensitive;
315 PG4SPCIH = 0x0;
316 // PSS Tied to 0; PPS Not inverted; SWTERM disabled; PSYNC disabled; TERM Manual Terminate; AQPS Not inverted; AQSS None; TSYNCDIS PWM EOC;
317 PG4SPCIL = 0x0;
318 // TRSET disabled; UPDREQ disabled; CLEVT disabled; TRCLR disabled; CAP disabled; SEVT disabled; FFEVT disabled; UPDATE disabled; FLTEVT disabled;
319 PG4STAT = 0x0;
320 // TRIGA4 0;
321 PG4TRIGA = 0x0;
322 // TRIGB4 0;
323 PG4TRIGB = 0x0;
324 // TRIGC4 0;
325 PG4TRIGC = 0x0;
326 // CTB3EN disabled; CTB2EN disabled; CTB1EN disabled; CTB4EN disabled; CTB8EN disabled; CTB7EN disabled; CTB6EN disabled; CTB5EN disabled;
327 CMBTRIGH = 0x0;
328 // CTA1EN disabled; CTA2EN disabled; CTA3EN disabled; CTA4EN disabled; CTA7EN disabled; CTA8EN disabled; CTA5EN disabled; CTA6EN disabled;
329 CMBTRIGL = 0x0;
330 // FSCL 0x0;
331 FSCL = 0x0;
332 // FSMINPER 0x0;
333 FSMINPER = 0x0;
334 // LFSR 0x0;
335 LFSR = 0x0;
336 // PWMLFA PWMS1 or PWMS2;; S1APOL Positive logic; S2APOL Positive logic; PWMLFAD No Assignment; PWMS1A PWM1H; PWMS2A PWM1H;
337 LOGCONA = 0x0;
338 // PWMLFB PWMS1 | PWMS2; S2BPOL Positive logic; PWMLFBD No Assignment; S1BPOL Positive logic; PWMS2B PWM1H; PWMS1B PWM1H;
339 LOGCONB = 0x0;
340 // PWMLFC PWMS1 | PWMS2; PWMLFCD No Assignment; S2CPOL Positive logic; S1CPOL Positive logic; PWMS1C PWM1H; PWMS2C PWM1H;
341 LOGCONC = 0x0;
342 // PWMS1D PWM1H; S1DPOL Positive logic; PWMLFD PWMS1 | PWMS2; PWMLFDD No Assignment; S2DPOL Positive logic; PWMS2D PWM1H;
343 LOGCOND = 0x0;
344 // PWMS1E PWM1H; PWMS2E PWM1H; S1EPOL Positive logic; PWMLFE PWMS1 | PWMS2; S2EPOL Positive logic; PWMLFED No Assignment;
345 LOGCONE = 0x0;
346 // S1FPOL Positive logic; PWMS2F PWM1H; PWMS1F PWM1H; S2FPOL Positive logic; PWMLFFD No Assignment; PWMLFF PWMS1 | PWMS2;
347 LOGCONF = 0x0;
348 // MDC 0;
349 MDC = 0x0;
350 // MPER 16;
351 MPER = 0x10;
352 // MPHASE 0x0;
353 MPHASE = 0x0;
354 // MCLKSEL AFVCO/2; LOCK disabled; DIVSEL 1:2; HRERR disabled;
355 PCLKCON = 0x1;
356 // EVTASEL PGTRGSEL bits; EVTASYNC Not synchronized; EVTAPOL Active-high; EVTAPGS PG1; EVTASTRD Stretched to 8 PWM clock cycles minimum; EVT1OEN disabled;
357 PWMEVTA = 0x0;
358 // EVTBPGS PG1; EVTBSYNC Not synchronized; EVTBPOL Active-high; EVTBSEL PGTRGSEL bits; EVTBSTRD Stretched to 8 PWM clock cycles minimum; EVT2OEN disabled;
359 PWMEVTB = 0x0;
360 // EVTCPGS PG1; EVTCPOL Active-high; EVTCSEL PGTRGSEL bits; EVTCSTRD Stretched to 8 PWM clock cycles minimum; EVTCSYNC Not synchronized; EVT3OEN disabled;
361 PWMEVTC = 0x0;
362 // EVT4OEN disabled; EVTDSTRD Stretched to 8 PWM clock cycles minimum; EVTDPOL Active-high; EVTDPGS PG1; EVTDSEL PGTRGSEL bits; EVTDSYNC Not synchronized;
363 PWMEVTD = 0x0;
364 // EVT5OEN disabled; EVTEPOL Active-high; EVTEPGS PG1; EVTESTRD Stretched to 8 PWM clock cycles minimum; EVTESEL PGTRGSEL bits; EVTESYNC Not synchronized;
365 PWMEVTE = 0x0;
366 // EVTFPOL Active-high; EVTFPGS PG1; EVTFSTRD Stretched to 8 PWM clock cycles minimum; EVTFSEL PGTRGSEL bits; EVT6OEN disabled; EVTFSYNC Not synchronized;
367 PWMEVTF = 0x0;
368
369 PWM_GeneratorEOCEventCallbackRegister(&PWM_GeneratorEOCEventCallback);
370
371
372
373}
374
375void PWM_Deinitialize (void)
376{
377 PWM_Disable();
378
379 PG1CONL = 0x0;
380 PG2CONL = 0x0;
381 PG3CONL = 0x0;
382 PG4CONL = 0x0;
383
384 PG1CAP = 0x0;
385 PG1CLPCIH = 0x0;
386 PG1CLPCIL = 0x0;
387 PG1CONH = 0x0;
388 PG1DC = 0x0;
389 PG1DCA = 0x0;
390 PG1DTH = 0x0;
391 PG1DTL = 0x0;
392 PG1EVTH = 0x0;
393 PG1EVTL = 0x0;
394 PG1FFPCIH = 0x0;
395 PG1FFPCIL = 0x0;
396 PG1FPCIH = 0x0;
397 PG1FPCIL = 0x0;
398 PG1IOCONH = 0x0;
399 PG1IOCONL = 0x0;
400 PG1LEBH = 0x0;
401 PG1LEBL = 0x0;
402 PG1PER = 0x0;
403 PG1PHASE = 0x0;
404 PG1SPCIH = 0x0;
405 PG1SPCIL = 0x0;
406 PG1STAT = 0x0;
407 PG1TRIGA = 0x0;
408 PG1TRIGB = 0x0;
409 PG1TRIGC = 0x0;
410 PG2CAP = 0x0;
411 PG2CLPCIH = 0x0;
412 PG2CLPCIL = 0x0;
413 PG2CONH = 0x0;
414 PG2DC = 0x0;
415 PG2DCA = 0x0;
416 PG2DTH = 0x0;
417 PG2DTL = 0x0;
418 PG2EVTH = 0x0;
419 PG2EVTL = 0x0;
420 PG2FFPCIH = 0x0;
421 PG2FFPCIL = 0x0;
422 PG2FPCIH = 0x0;
423 PG2FPCIL = 0x0;
424 PG2IOCONH = 0x0;
425 PG2IOCONL = 0x0;
426 PG2LEBH = 0x0;
427 PG2LEBL = 0x0;
428 PG2PER = 0x0;
429 PG2PHASE = 0x0;
430 PG2SPCIH = 0x0;
431 PG2SPCIL = 0x0;
432 PG2STAT = 0x0;
433 PG2TRIGA = 0x0;
434 PG2TRIGB = 0x0;
435 PG2TRIGC = 0x0;
436 PG3CAP = 0x0;
437 PG3CLPCIH = 0x0;
438 PG3CLPCIL = 0x0;
439 PG3CONH = 0x0;
440 PG3DC = 0x0;
441 PG3DCA = 0x0;
442 PG3DTH = 0x0;
443 PG3DTL = 0x0;
444 PG3EVTH = 0x0;
445 PG3EVTL = 0x0;
446 PG3FFPCIH = 0x0;
447 PG3FFPCIL = 0x0;
448 PG3FPCIH = 0x0;
449 PG3FPCIL = 0x0;
450 PG3IOCONH = 0x0;
451 PG3IOCONL = 0x0;
452 PG3LEBH = 0x0;
453 PG3LEBL = 0x0;
454 PG3PER = 0x0;
455 PG3PHASE = 0x0;
456 PG3SPCIH = 0x0;
457 PG3SPCIL = 0x0;
458 PG3STAT = 0x0;
459 PG3TRIGA = 0x0;
460 PG3TRIGB = 0x0;
461 PG3TRIGC = 0x0;
462 PG4CAP = 0x0;
463 PG4CLPCIH = 0x0;
464 PG4CLPCIL = 0x0;
465 PG4CONH = 0x0;
466 PG4DC = 0x0;
467 PG4DCA = 0x0;
468 PG4DTH = 0x0;
469 PG4DTL = 0x0;
470 PG4EVTH = 0x0;
471 PG4EVTL = 0x0;
472 PG4FFPCIH = 0x0;
473 PG4FFPCIL = 0x0;
474 PG4FPCIH = 0x0;
475 PG4FPCIL = 0x0;
476 PG4IOCONH = 0x0;
477 PG4IOCONL = 0x0;
478 PG4LEBH = 0x0;
479 PG4LEBL = 0x0;
480 PG4PER = 0x0;
481 PG4PHASE = 0x0;
482 PG4SPCIH = 0x0;
483 PG4SPCIL = 0x0;
484 PG4STAT = 0x0;
485 PG4TRIGA = 0x0;
486 PG4TRIGB = 0x0;
487 PG4TRIGC = 0x0;
488 CMBTRIGH = 0x0;
489 CMBTRIGL = 0x0;
490 FSCL = 0x0;
491 FSMINPER = 0x0;
492 LFSR = 0x0;
493 LOGCONA = 0x0;
494 LOGCONB = 0x0;
495 LOGCONC = 0x0;
496 LOGCOND = 0x0;
497 LOGCONE = 0x0;
498 LOGCONF = 0x0;
499 MDC = 0x0;
500 MPER = 0x0;
501 MPHASE = 0x0;
502 PCLKCON = 0x0;
503 PWMEVTA = 0x0;
504 PWMEVTB = 0x0;
505 PWMEVTC = 0x0;
506 PWMEVTD = 0x0;
507 PWMEVTE = 0x0;
508 PWMEVTF = 0x0;
509}
510
511void PWM_GeneratorEOCEventCallbackRegister(void (*callback)(enum PWM_GENERATOR genNum))
512{
513 if(NULL != callback)
514 {
515 PWM_GeneratorEOCEventHandler = callback;
516 }
517}
518
519void __attribute__ ((weak)) PWM_GeneratorEOCEventCallback ( enum PWM_GENERATOR genNum )
520{
521
522}
523
524
525void PWM_GeneratorTasks (enum PWM_GENERATOR intGen)
526{
527 switch(intGen)
528 {
529 case PWM_PRI_1:
530 if(IFS4bits.PWM1IF == 1)
531 {
532 if(NULL != PWM_GeneratorEOCEventHandler)
533 {
534 (*PWM_GeneratorEOCEventHandler)(intGen);
535 }
536 IFS4bits.PWM1IF = 0;
537 }
538 break;
539 case PWM_SEC_1:
540 if(IFS4bits.PWM2IF == 1)
541 {
542 if(NULL != PWM_GeneratorEOCEventHandler)
543 {
544 (*PWM_GeneratorEOCEventHandler)(intGen);
545 }
546 IFS4bits.PWM2IF = 0;
547 }
548 break;
549 case PWM_PRI_2:
550 if(IFS4bits.PWM3IF == 1)
551 {
552 if(NULL != PWM_GeneratorEOCEventHandler)
553 {
554 (*PWM_GeneratorEOCEventHandler)(intGen);
555 }
556 IFS4bits.PWM3IF = 0;
557 }
558 break;
559 case PWM_SEC_2:
560 if(IFS4bits.PWM4IF == 1)
561 {
562 if(NULL != PWM_GeneratorEOCEventHandler)
563 {
564 (*PWM_GeneratorEOCEventHandler)(intGen);
565 }
566 IFS4bits.PWM4IF = 0;
567 }
568 break;
569 default:
570 break;
571 }
572}
573
pwm.h
This is the generated driver header file for the PWM driver.
PWM_SEC_1
@ PWM_SEC_1
Definition pwm_hs_types.h:56
PWM_PRI_1
@ PWM_PRI_1
Definition pwm_hs_types.h:55
PWM_SEC_2
@ PWM_SEC_2
Definition pwm_hs_types.h:58
PWM_PRI_2
@ PWM_PRI_2
Definition pwm_hs_types.h:57
__attribute__
void __attribute__((weak))
Definition pwm.c:519
PWM_GeneratorEOCEventHandler
static void(* PWM_GeneratorEOCEventHandler)(enum PWM_GENERATOR genNum)
Definition pwm.c:45
PWM_Trigger2Enable
static void PWM_Trigger2Enable(enum PWM_GENERATOR genNum, enum PWM_TRIGGER_COMPARE compareRegister)
This inline function enables ADC trigger 2 for the specific compare register selected by the argument...
Definition pwm.h:1527
PWM_MasterPhaseSet
static void PWM_MasterPhaseSet(uint16_t masterPhase)
This inline function sets the phase value in count for the Master Time Base generator.
Definition pwm.h:462
PWM_GeneratorInterruptDisable
static void PWM_GeneratorInterruptDisable(enum PWM_GENERATOR genNum, enum PWM_GENERATOR_INTERRUPT interrupt)
This inline function disables interrupt requests for the PWM Generator selected by the argument PWM_G...
Definition pwm.h:988
PWM_DeadTimeLowSet
static void PWM_DeadTimeLowSet(enum PWM_GENERATOR genNum, uint16_t deadtimeLow)
This inline function updates PWM Deadtime low register with the requested value for a specific PWM ge...
Definition pwm.h:793
PWM_OverrideDataHighSet
static void PWM_OverrideDataHighSet(enum PWM_GENERATOR genNum, bool overrideDataHigh)
This inline function updates PWM override high data bit with the requested value for a specific PWM g...
Definition pwm.h:606
PWM_Trigger1Disable
static void PWM_Trigger1Disable(enum PWM_GENERATOR genNum, enum PWM_TRIGGER_COMPARE compareRegister)
This inline function disables ADC trigger 1 for the specific compare register selected by the argumen...
Definition pwm.h:1452
PWM_OverrideDataGet
static uint16_t PWM_OverrideDataGet(enum PWM_GENERATOR genNum)
This inline function gets PWM override value for the PWM Generator selected by the argument PWM_GENER...
Definition pwm.h:660
PWM_OverrideLowEnable
static void PWM_OverrideLowEnable(enum PWM_GENERATOR genNum)
This inline function enables PWM override on PWML output for specific PWM generator selected by the a...
Definition pwm.h:714
PWM_HS
const struct PWM_HS_INTERFACE PWM_HS
Structure object of type PWM_HS_INTERFACE with the custom name given by the user in the Melody Driver...
Definition pwm.c:50
PWM_Initialize
void PWM_Initialize(void)
Initializes PWM module, using the given initialization data.
Definition pwm.c:108
PWM_MasterPeriodSet
static void PWM_MasterPeriodSet(uint16_t masterPeriod)
This inline function sets the period value in count for the Master Time Base generator.
Definition pwm.h:440
PWM_TriggerACompareValueSet
static void PWM_TriggerACompareValueSet(enum PWM_GENERATOR genNum, uint16_t trigA)
This inline function sets the Trigger A compare value in count for a specific PWM generator selected ...
Definition pwm.h:1296
PWM_TriggerBCompareValueSet
static void PWM_TriggerBCompareValueSet(enum PWM_GENERATOR genNum, uint16_t trigB)
This inline function sets the Trigger B compare value in count for a specific PWM generator selected ...
Definition pwm.h:1323
PWM_DutyCycleSet
static void PWM_DutyCycleSet(enum PWM_GENERATOR genNum, uint16_t dutyCycle)
This inline function sets the PWM generator specific duty cycle register.
Definition pwm.h:500
PWM_GeneratorEOCEventCallback
void PWM_GeneratorEOCEventCallback(enum PWM_GENERATOR genNum)
This is the default callback with weak attribute. The user can override and implement the default cal...
PWM_Deinitialize
void PWM_Deinitialize(void)
Deinitializes the PWM to POR values.
Definition pwm.c:375
PWM_TriggerCompareValueSet
static void PWM_TriggerCompareValueSet(enum PWM_GENERATOR genNum, uint16_t trigCompValue)
This inline function sets the PWM trigger compare value in count for the PWM Generator selected by th...
Definition pwm.h:878
PWM_OverrideHighEnable
static void PWM_OverrideHighEnable(enum PWM_GENERATOR genNum)
This inline function enables PWM override on PWMH output for specific PWM generator selected by the a...
Definition pwm.h:688
PWM_GeneratorDisable
static void PWM_GeneratorDisable(enum PWM_GENERATOR genNum)
This inline function disables the specific PWM generator selected by the argument PWM_GENERATOR.
Definition pwm.h:328
PWM_Disable
static void PWM_Disable(void)
This inline function will disable all the generators of PWM module.
Definition pwm.h:426
PWM_PhaseSet
static void PWM_PhaseSet(enum PWM_GENERATOR genNum, uint16_t phase)
This inline function sets the phase value in count for the PWM generator specific Time Base.
Definition pwm.h:552
PWM_GeneratorEventStatusGet
static bool PWM_GeneratorEventStatusGet(enum PWM_GENERATOR genNum, enum PWM_GENERATOR_INTERRUPT interrupt)
This inline function gets the PWM interrupt status for the PWM Generator selected by the argument PWM...
Definition pwm.h:1155
PWM_FaultModeLatchClear
static void PWM_FaultModeLatchClear(enum PWM_GENERATOR genNum)
This inline function clears the status of PWM latched fault mode for the PWM Generator selected by th...
Definition pwm.h:1670
PWM_ModeSet
static void PWM_ModeSet(enum PWM_GENERATOR genNum, enum PWM_MODES mode)
This inline function sets the operating mode of specific PWM generator selected by the argument PWM...
Definition pwm.h:355
PWM_SoftwareUpdateRequest
static void PWM_SoftwareUpdateRequest(enum PWM_GENERATOR genNum)
This inline function requests to update the data registers for specific PWM generator selected by the...
Definition pwm.h:1239
PWM_MasterDutyCycleSet
static void PWM_MasterDutyCycleSet(uint16_t masterDutyCycle)
This inline function sets the PWM master duty cycle register.
Definition pwm.h:451
PWM_OverrideDataLowSet
static void PWM_OverrideDataLowSet(enum PWM_GENERATOR genNum, bool overrideDataLow)
This inline function updates PWM override low data bit with the requested value for a specific PWM ge...
Definition pwm.h:633
PWM_OverrideHighDisable
static void PWM_OverrideHighDisable(enum PWM_GENERATOR genNum)
This inline function disables PWM override on PWMH output for specific PWM generator selected by the ...
Definition pwm.h:740
PWM_OverrideDataSet
static void PWM_OverrideDataSet(enum PWM_GENERATOR genNum, uint16_t overrideData)
This inline function updates PWM override data bits with the requested value for a specific PWM gener...
Definition pwm.h:579
PWM_DeadTimeSet
static void PWM_DeadTimeSet(enum PWM_GENERATOR genNum, uint16_t deadtime)
This inline function updates PWM Deadtime low and high register with the requested value for a specif...
Definition pwm.h:847
PWM_GENERATOR
PWM_GENERATOR
Defines the PWM generators that are selected from the MCC Melody User Interface for the PWM output co...
Definition pwm_hs_types.h:54
PWM_SoftwareUpdatePending
static bool PWM_SoftwareUpdatePending(enum PWM_GENERATOR genNum)
This inline function gets the status of the update request for specific PWM generator selected by the...
Definition pwm.h:1267
PWM_GeneratorTasks
void PWM_GeneratorTasks(enum PWM_GENERATOR intGen)
This is a tasks function for PWM1.
Definition pwm.c:525
PWM_Trigger2Disable
static void PWM_Trigger2Disable(enum PWM_GENERATOR genNum, enum PWM_TRIGGER_COMPARE compareRegister)
This inline function disables ADC trigger 2 for the specific compare register selected by the argumen...
Definition pwm.h:1599
PWM_GeneratorEventStatusClear
static void PWM_GeneratorEventStatusClear(enum PWM_GENERATOR genNum, enum PWM_GENERATOR_INTERRUPT interrupt)
This inline function clears the PWM interrupt status for the PWM Generator selected by the argument P...
Definition pwm.h:1071
PWM_OverrideLowDisable
static void PWM_OverrideLowDisable(enum PWM_GENERATOR genNum)
This inline function disables PWM override on PWML output for specific PWM generator selected by the ...
Definition pwm.h:766
PWM_GeneratorInterruptEnable
static void PWM_GeneratorInterruptEnable(enum PWM_GENERATOR genNum, enum PWM_GENERATOR_INTERRUPT interrupt)
This inline function enables interrupt requests for the PWM Generator selected by the argument PWM_GE...
Definition pwm.h:905
PWM_TriggerCCompareValueSet
static void PWM_TriggerCCompareValueSet(enum PWM_GENERATOR genNum, uint16_t trigC)
This inline function sets the Trigger C compare value in count for a specific PWM generator selected ...
Definition pwm.h:1350
PWM_PhaseSelect
static void PWM_PhaseSelect(enum PWM_GENERATOR genNum, enum PWM_SOURCE_SELECT source)
This inline function selects the PWM generator source for Phase.
Definition pwm.h:526
PWM_Trigger1Enable
static void PWM_Trigger1Enable(enum PWM_GENERATOR genNum, enum PWM_TRIGGER_COMPARE compareRegister)
This inline function enables ADC trigger 1 for the specific compare register selected by the argument...
Definition pwm.h:1380
PWM_PeriodSet
static void PWM_PeriodSet(enum PWM_GENERATOR genNum, uint16_t period)
This inline function sets the period value in count for the PWM generator specific Time Base.
Definition pwm.h:474
PWM_GeneratorEnable
static void PWM_GeneratorEnable(enum PWM_GENERATOR genNum)
This inline function enables the specific PWM generator selected by the argument PWM_GENERATOR.
Definition pwm.h:302
PWM_DeadTimeHighSet
static void PWM_DeadTimeHighSet(enum PWM_GENERATOR genNum, uint16_t deadtimeHigh)
This inline function updates PWM Deadtime high register with the requested value for a specific PWM g...
Definition pwm.h:820
PWM_Enable
static void PWM_Enable(void)
This inline function will enable all the generators of PWM module.
Definition pwm.h:412
PWM_GeneratorEOCEventCallbackRegister
void PWM_GeneratorEOCEventCallbackRegister(void(*callback)(enum PWM_GENERATOR genNum))
This function can be used to override default callback PWM_GeneratorEOCEventCallback and to define cu...
Definition pwm.c:511
PWM_HS_INTERFACE
Structure containing the function pointers of PWM driver.
Definition pwm_hs_interface.h:56