Bar Logo 3.8/7.6 kw Totem pole Demonstration Application (Part-No. (not specified))
 
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config_bits.c
1
17/*
18© [2024] Microchip Technology Inc. and its subsidiaries.
19
20 Subject to your compliance with these terms, you may use Microchip
21 software and any derivatives exclusively with Microchip products.
22 You are responsible for complying with 3rd party license terms
23 applicable to your use of 3rd party software (including open source
24 software) that may accompany Microchip software. SOFTWARE IS ?AS IS.?
25 NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS
26 SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT,
27 MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT
28 WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
29 INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY
30 KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
31 MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE
32 FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP?S
33 TOTAL LIABILITY ON ALL CLAIMS RELATED TO THE SOFTWARE WILL NOT
34 EXCEED AMOUNT OF FEES, IF ANY, YOU PAID DIRECTLY TO MICROCHIP FOR
35 THIS SOFTWARE.
36*/
37
38// Configuration bits: selected in the GUI
39
40// FSEC
41#pragma config BWRP = OFF //Boot Segment Write-Protect bit->Boot Segment may be written
42#pragma config BSS = DISABLED //Boot Segment Code-Protect Level bits->No Protection (other than BWRP)
43#pragma config BSEN = OFF //Boot Segment Control bit->No Boot Segment
44#pragma config GWRP = OFF //General Segment Write-Protect bit->General Segment may be written
45#pragma config GSS = DISABLED //General Segment Code-Protect Level bits->No Protection (other than GWRP)
46#pragma config CWRP = OFF //Configuration Segment Write-Protect bit->Configuration Segment may be written
47#pragma config CSS = DISABLED //Configuration Segment Code-Protect Level bits->No Protection (other than CWRP)
48#pragma config AIVTDIS = OFF //Alternate Interrupt Vector Table bit->Disabled AIVT
49
50// FBSLIM
51#pragma config BSLIM = 0x1fff //Boot Segment Flash Page Address Limit bits
52
53// FOSCSEL
54#pragma config FNOSC = FRC //Oscillator Source Selection->Internal Fast RC (FRC)
55#pragma config IESO = OFF //Two-speed Oscillator Start-up Enable bit->Start up with user-selected oscillator source
56
57// FOSC
58#pragma config POSCMD = EC //Primary Oscillator Mode Select bits->EC (External Clock) Mode
59#pragma config OSCIOFNC = ON //OSC2 Pin Function bit->OSC2 is general purpose digital I/O pin
60#pragma config FCKSM = CSECMD //Clock Switching Mode bits->Clock switching is enabled,Fail-safe Clock Monitor is disabled
61#pragma config PLLKEN = PLLKEN_ON //PLL Lock Status Control->PLL lock signal will be used to disable PLL clock output if lock is lost
62#pragma config XTCFG = G3 //XT Config->24-32 MHz crystals
63#pragma config XTBST = ENABLE //XT Boost->Boost the kick-start
64
65// FWDT
66#pragma config RWDTPS = PS1048576 //Run Mode Watchdog Timer Post Scaler select bits->1:1048576
67#pragma config RCLKSEL = LPRC //Watchdog Timer Clock Select bits->Always use LPRC
68#pragma config WINDIS = ON //Watchdog Timer Window Enable bit->Watchdog Timer in Non-Window mode
69#pragma config WDTWIN = WIN25 //Watchdog Timer Window Select bits->WDT Window is 25% of WDT period
70#pragma config SWDTPS = PS1048576 //Sleep Mode Watchdog Timer Post Scaler select bits->1:1048576
71#pragma config FWDTEN = ON_SW //Watchdog Timer Enable bit->WDT controlled via SW, use WDTCON.ON bit
72
73// FPOR
74#pragma config BISTDIS = DISABLED //Memory BIST Feature Disable->mBIST on reset feature disabled
75
76// FICD
77#pragma config ICS = PGD2 //ICD Communication Channel Select bits->Communicate on PGC2 and PGD2
78#pragma config JTAGEN = OFF //JTAG Enable bit->JTAG is disabled
79#pragma config NOBTSWP = OFF //BOOTSWP instruction disable bit->BOOTSWP instruction is disabled
80
81// FDMTIVTL
82#pragma config DMTIVTL = 0x0 //Dead Man Timer Interval low word
83
84// FDMTIVTH
85#pragma config DMTIVTH = 0x0 //Dead Man Timer Interval high word
86
87// FDMTCNTL
88#pragma config DMTCNTL = 0x0 //Lower 16 bits of 32 bit DMT instruction count time-out value (0-0xFFFF)
89
90// FDMTCNTH
91#pragma config DMTCNTH = 0x0 //Upper 16 bits of 32 bit DMT instruction count time-out value (0-0xFFFF)
92
93// FDMT
94#pragma config DMTDIS = OFF //Dead Man Timer Disable bit->Dead Man Timer is Disabled and can be enabled by software
95
96// FDEVOPT
97#pragma config ALTI2C1 = OFF //Alternate I2C1 Pin bit->I2C1 mapped to SDA1/SCL1 pins
98#pragma config ALTI2C2 = OFF //Alternate I2C2 Pin bit->I2C2 mapped to SDA2/SCL2 pins
99#pragma config SMBEN = SMBUS //SM Bus Enable->SMBus input threshold is enabled
100#pragma config SPI2PIN = PPS //SPI2 Pin Select bit->SPI2 uses I/O remap (PPS) pins
101
102// FALTREG
103#pragma config CTXT1 = OFF //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits->Not Assigned
104#pragma config CTXT2 = OFF //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 2 bits->Not Assigned
105#pragma config CTXT3 = OFF //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 3 bits->Not Assigned
106#pragma config CTXT4 = OFF //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 4 bits->Not Assigned
107
108// FCFGPRA0
109#pragma config CPRA0 = MAIN //Pin RA0 Ownership Bits->Main core owns pin.
110#pragma config CPRA1 = SEC1 //Pin RA1 Ownership Bits->Secondary core owns pin.
111#pragma config CPRA2 = MAIN //Pin RA2 Ownership Bits->Main core owns pin.
112#pragma config CPRA3 = SEC1 //Pin RA3 Ownership Bits->Secondary core owns pin.
113#pragma config CPRA4 = SEC1 //Pin RA4 Ownership Bits->Secondary core owns pin.
114
115// FCFGPRB0
116#pragma config CPRB0 = MAIN //Pin RB0 Ownership Bits->Main core owns pin.
117#pragma config CPRB1 = MAIN //Pin RB1 Ownership Bits->Main core owns pin.
118#pragma config CPRB2 = SEC1 //Pin RB2 Ownership Bits->Secondary core owns pin.
119#pragma config CPRB3 = MAIN //Pin RB3 Ownership Bits->Main core owns pin.
120#pragma config CPRB4 = MAIN //Pin RB4 Ownership Bits->Main core owns pin.
121#pragma config CPRB5 = MAIN //Pin RB5 Ownership Bits->Main core owns pin.
122#pragma config CPRB6 = MAIN //Pin RB6 Ownership Bits->Main core owns pin.
123#pragma config CPRB7 = MAIN //Pin RB7 Ownership Bits->Main core owns pin.
124#pragma config CPRB8 = MAIN //Pin RB8 Ownership Bits->Main core owns pin.
125#pragma config CPRB9 = MAIN //Pin RB9 Ownership Bits->Main core owns pin.
126#pragma config CPRB10 = MAIN //Pin RB10 Ownership Bits->Main core owns pin.
127#pragma config CPRB11 = MAIN //Pin RB11 Ownership Bits->Main core owns pin.
128#pragma config CPRB12 = MAIN //Pin RB12 Ownership Bits->Main core owns pin.
129#pragma config CPRB13 = SEC1 //Pin RB13 Ownership Bits->Secondary core owns pin.
130#pragma config CPRB14 = SEC1 //Pin RB14 Ownership Bits->Secondary core owns pin.
131#pragma config CPRB15 = MAIN //Pin RB15 Ownership Bits->Main core owns pin.
132
133// FCFGPRC0
134#pragma config CPRC0 = SEC1 //Pin RC0 Ownership Bits->Secondary core owns pin.
135#pragma config CPRC1 = MAIN //Pin RC1 Ownership Bits->Main core owns pin.
136#pragma config CPRC2 = MAIN //Pin RC2 Ownership Bits->Main core owns pin.
137#pragma config CPRC3 = SEC1 //Pin RC3 Ownership Bits->Secondary core owns pin.
138#pragma config CPRC4 = SEC1 //Pin RC4 Ownership Bits->Secondary core owns pin.
139#pragma config CPRC5 = SEC1 //Pin RC5 Ownership Bits->Secondary core owns pin.
140#pragma config CPRC6 = SEC1 //Pin RC6 Ownership Bits->Secondary core owns pin.
141#pragma config CPRC7 = SEC1 //Pin RC7 Ownership Bits->Secondary core owns pin.
142#pragma config CPRC8 = MAIN //Pin RC8 Ownership Bits->Main core owns pin.
143#pragma config CPRC9 = SEC1 //Pin RC9 Ownership Bits->Secondary core owns pin.
144#pragma config CPRC10 = SEC1 //Pin RC10 Ownership Bits->Secondary core owns pin.
145#pragma config CPRC11 = SEC1 //Pin RC11 Ownership Bits->Secondary core owns pin.
146#pragma config CPRC12 = SEC1 //Pin RC12 Ownership Bits->Secondary core owns pin.
147#pragma config CPRC13 = SEC1 //Pin RC13 Ownership Bits->Secondary core owns pin.
148#pragma config CPRC14 = SEC1 //Pin RC14 Ownership Bits->Secondary core owns pin.
149#pragma config CPRC15 = SEC1 //Pin RC15 Ownership Bits->Secondary core owns pin.
150
151// FCFGPRD0
152#pragma config CPRD0 = SEC1 //Pin RD0 Ownership Bits->Secondary core owns pin.
153#pragma config CPRD1 = SEC1 //Pin RD1 Ownership Bits->Secondary core owns pin.
154#pragma config CPRD2 = SEC1 //Pin RD2 Ownership Bits->Secondary core owns pin.
155#pragma config CPRD3 = SEC1 //Pin RD3 Ownership Bits->Secondary core owns pin.
156#pragma config CPRD4 = SEC1 //Pin RD4 Ownership Bits->Secondary core owns pin.
157#pragma config CPRD5 = SEC1 //Pin RD5 Ownership Bits->Secondary core owns pin.
158#pragma config CPRD6 = SEC1 //Pin RD6 Ownership Bits->Secondary core owns pin.
159#pragma config CPRD7 = MAIN //Pin RD7 Ownership Bits->Main core owns pin.
160#pragma config CPRD8 = SEC1 //Pin RD8 Ownership Bits->Secondary core owns pin.
161#pragma config CPRD9 = SEC1 //Pin RD9 Ownership Bits->Secondary core owns pin.
162#pragma config CPRD10 = SEC1 //Pin RD10 Ownership Bits->Secondary core owns pin.
163#pragma config CPRD11 = SEC1 //Pin RD11 Ownership Bits->Secondary core owns pin.
164#pragma config CPRD12 = MAIN //Pin RD12 Ownership Bits->Main core owns pin.
165#pragma config CPRD13 = SEC1 //Pin RD13 Ownership Bits->Secondary core owns pin.
166#pragma config CPRD14 = SEC1 //Pin RD14 Ownership Bits->Secondary core owns pin.
167#pragma config CPRD15 = MAIN //Pin RD15 Ownership Bits->Main core owns pin.
168
169// FCFGPRE0
170#pragma config CPRE0 = MAIN //Pin RE0 Ownership Bits->Main core owns pin.
171#pragma config CPRE1 = MAIN //Pin RE1 Ownership Bits->Main core owns pin.
172#pragma config CPRE2 = MAIN //Pin RE2 Ownership Bits->Main core owns pin.
173#pragma config CPRE3 = MAIN //Pin RE3 Ownership Bits->Main core owns pin.
174#pragma config CPRE4 = MAIN //Pin RE4 Ownership Bits->Main core owns pin.
175#pragma config CPRE5 = MAIN //Pin RE5 Ownership Bits->Main core owns pin.
176#pragma config CPRE6 = MAIN //Pin RE6 Ownership Bits->Main core owns pin.
177#pragma config CPRE7 = MAIN //Pin RE7 Ownership Bits->Main core owns pin.
178#pragma config CPRE8 = MAIN //Pin RE8 Ownership Bits->Main core owns pin.
179#pragma config CPRE9 = MAIN //Pin RE9 Ownership Bits->Main core owns pin.
180#pragma config CPRE10 = MAIN //Pin RE10 Ownership Bits->Main core owns pin.
181#pragma config CPRE11 = MAIN //Pin RE11 Ownership Bits->Main core owns pin.
182#pragma config CPRE12 = MAIN //Pin RE12 Ownership Bits->Main core owns pin.
183#pragma config CPRE13 = MAIN //Pin RE13 Ownership Bits->Main core owns pin.
184#pragma config CPRE14 = MAIN //Pin RE14 Ownership Bits->Main core owns pin.
185#pragma config CPRE15 = MAIN //Pin RE15 Ownership Bits->Main core owns pin.
186
187// FBTSEQ
188#pragma config BSEQ = 0xfff //Relative value defining which partition will be active after devie Reset; the partition containing a lower boot number will be active.
189#pragma config IBSEQ = 0xfff //The one's complement of BSEQ; must be calculated by the user and written during device programming.
190
191// FBOOT
192#pragma config BTMODE = SINGLE //Device Boot Mode Configuration->Device is in Single Boot (legacy) mode
193
196