Device Start Up

Device Start Up. More...

Collaboration diagram for Device Start Up:

Modules
	Initializing Essential Chip Resources
	Initializing Hardware-Specific Chip Resources
	Initializing Firmware Tasks

Detailed Description

Device Start Up.

When the device comes out of RESET, it is running off the selected oscillator at its natural frequency. The startup oscillator type is declared in the FOSCSEL register by setting the respective configuration bits (FUSES). FUSES (configuration bits) can only be set at compile time before the settings are programmed into the device.

#pragma config FNOSC = FRCDIVN 

• Step 1 (System Initialization):
  
  The first step focuses on essential IC resources only, such as oscillator and device inputs/outputs. The following modules are initialized in the given order:
  
  
  • Main Oscillator:
    In this design the internal 8 MHz RC oscillator is used. Hence, the very first step in the firmware is to set up the internal PLL to operate the CPU at maximum speed of 100 MIPS (100 MHz instruction cycle).
    
    
  • Auxiliary Oscillator:
    The Auxiliary Oscillator is a second PLL, which can be set up to a different frequency than the main oscillator and provided to peripheral modules. This auxiliary clock signal is used by the PWM and ADC module to perform at maximum speed and performance. In this design, the auxiliary clock is set up for 500 MHz base clock.
    
    
  • GPIO Reset:
    To make sure there are no conflicts with individual application tasks and related peripheral configurations, all General Purpose Inputs/Outputs (GPIOs) are set as digital inputs with its internal control signals set LOW.
    
    
  • Digital Signal Processor Logic (DSP):
    The internal Digital Signal Processing (DSP) engine is configured for fractional multiplication with saturation enabled. This configuration is optimized for control loop computations. The control loops are able to self-manage their required DSP configuration, however, this would add execution cycles and increase the overall CPU load. As no other task/process in this application uses the DSP, the DSP configuration has been taken out of the control loop CPU configuration self-management and added to the system initialization of the project as static configuration to reduce the overall CPU workload.
    
    
• Step 2 (User Peripheral Initialization):
  
  The second step initializes user-defined peripherals, which are not managed by any other part of the application. The following modules are initialized in the given order:
  
  
  • Digital-To-Analog Converter (DAC)
    This design requires an independent reference voltage to adjust external current sense shunt amplifier devices to offset their output voltage, allowing the monitoring of the full triangular inductor current waveform in discontinuous as well as continuous conduction mode. Each DAC module of dsPIC33 also includes an analog high-sped comparator, which is not used in this configuration.
    
    
  • Operational Amplifier (OPA)
    The internally generated reference voltage (see DAC configuration above) is buffered by using one of the on-chip Operational amplifiers. This section assigns the input pin to this op-amp and enables the output.
    
    
• Step 3 (User Peripheral Initialization):
  
  In the third step all tasks of the application are initialized by calling their default API INITIALIZE function. Each task module is self-managing and does not require additional parameters to be considered at this function call level. However, each task provides an individual application layer which is used to configure the task and all its implied settings and parameters. (Please refer to the documentation of each task for details.)
  
  
  • Power Control Task
    The Power Control Task covers the complete management of the included power supply circuit and control loops. This tasks utilizes a standard single- and multiphase buck converter library, which provides a complete runtime state-machine managing self-initialization, soft-start, soft-stop, runtime reference tuning and auto-restart. It also includes enhanced features such as automatic adjustment to pre-biased outputs, feedback offset compensation and supports different control modes such as voltage mode control (VMC) or average current mode control (ACMC).
    
    
  • Fault Monitor Task
    The Fault Monitor Task is a global task providing application-wide fault detection. The separation of power converter control and fault monitoring allows the consideration of application dependencies between tasks.
    
    

• Step 4 (OS Timer Initialization):
  
  In the fourth step the operating system time base is initialized. In this slim application the operating system consists of two different task execution levels on two priority levels:
  
  

  • Low-Priority Task Execution
    the low priority tasks are executed from a common function called sysLowPriorityTasks_Execute. This task layer is executed with lowest priority (=0).
    
    
  • High-Priority Task Execution
    High priority tasks are executed from the Timer Interrupt Service Routine (ISR) of the OS timebase timer. The interupt priority is set one above the low priority task level (default = 2). In this application the alternate working registers of the device have been configured to automatically switch context when the timer interrupt is triggered by setting FUSE CTXT1 = IPL2.

    #pragma config CTXT1 = IPL2