Digital Power Starter Kit 3 Firmware  DM330017-3, Rev.3.0
dsPIC33C Buck Converter Peak Current Mode Control Example
dev_buck_ptemp_dac.h
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21 
22 /*
23  * File: dev_buck_ptemp_dac.h
24  * Author: M91406
25  * Comments: DAC Peripheral Special Function Register Configuration Template
26  * Revision history:
27  * 10/29/2020 1.0 initial release
28  */
29 
30 // This is a guard condition so that contents of this file are not included
31 // more than once.
32 #ifndef BUCK_CONVERTER_PERIPHERAL_CONFIGURATION_DAC_H
33 #define BUCK_CONVERTER_PERIPHERAL_CONFIGURATION_DAC_H
34 
35 #include <xc.h> // include processor files - each processor file is guarded.
36 #include <stdint.h> // include standard integer data types
37 #include <stdbool.h> // include standard boolean data types
38 #include <stddef.h> // include standard definition data types
39 
45 /* ********************************************************************************
46  * DAC / COMPARATOR / SLOPE COMPENSATION INSTANCE CONFIGURATION
47  * *******************************************************************************/
52 /*
53 
54  ________________ BIT 15: DACEN: Individual DACx Module Enable
55  | _______________ BIT 14: IRQM[1:0]: Interrupt Mode select
56  || ______________ BIT 13:
57  ||| _____________ BIT 12: (unimplemented)
58  |||| ____________ BIT 11: (unimplemented)
59  ||||| ___________ BIT 10: CBE: Comparator Blank Enable
60  |||||| __________ BIT 9: DACOEN: DACx Output Buffer Enable
61  ||||||| _________ BIT 8: FLTREN: Comparator Digital Filter Enable
62  |||||||| ________ BIT 7: CMPSTAT: Comparator Status
63  ||||||||| _______ BIT 6: CMPPOL: Comparator Output Polarity Control
64  |||||||||| ______ BIT 5: INSEL[2:0]: Comparator Input Source Select
65  ||||||||||| _____ BIT 4:
66  |||||||||||| ____ BIT 3:
67  ||||||||||||| ___ BIT 2: HYSPOL: Comparator Hysteresis Polarity Select
68  |||||||||||||| __ BIT 1: HYSSEL[1:0]: Comparator Hysteresis Select
69  ||||||||||||||| _ BIT 0:
70  |||||||||||||||| */
71 #define REG_DACxCONL_PC 0b0000000000000110 // Peak Current Mode Configuration
72 #define REG_DACxCONL 0b0000000000000000 // Default Configuration
73 #define REG_DACOEN_EN 0b0000001000000000 // Register bit mask enabling the DAC output
78 /*
79 
80  ________________ BIT 15: (unimplemented)
81  | _______________ BIT 14: (unimplemented)
82  || ______________ BIT 13: (unimplemented)
83  ||| _____________ BIT 12: (unimplemented)
84  |||| ____________ BIT 11: (unimplemented)
85  ||||| ___________ BIT 10: (unimplemented)
86  |||||| __________ BIT 9: TMCB[9:0]: DACx Leading-Edge Blanking bits
87  ||||||| _________ BIT 8:
88  |||||||| ________ BIT 7:
89  ||||||||| _______ BIT 6:
90  |||||||||| ______ BIT 5:
91  ||||||||||| _____ BIT 4:
92  |||||||||||| ____ BIT 3:
93  ||||||||||||| ___ BIT 2:
94  |||||||||||||| __ BIT 1:
95  ||||||||||||||| _ BIT 0:
96  |||||||||||||||| */
97 #define REG_DACxCONH 0b0000000000000000 // Leading Edge Blanking period will be loaded during initialization
98 
99 /* DACxCONH: DACx CONTROL REGISTER HIGH => Timing Register: User value will be set in code */
100 /* DACxCONL: DACx CONTROL REGISTER LOW => Timing Register: User value will be set in code */
101 
106 /* SLPxCONL: DACx SLOPE CONTROL REGISTER LOW
107 
108  ________________ BIT 15: HCFSEL[3:0]: Hysteretic Comparator Function Input Selection
109  | _______________ BIT 14:
110  || ______________ BIT 13:
111  ||| _____________ BIT 12:
112  |||| ____________ BIT 11: SLPSTOPA[3:0]: Slope Stop A Signal Selection
113  ||||| ___________ BIT 10:
114  |||||| __________ BIT 9:
115  ||||||| _________ BIT 8:
116  |||||||| ________ BIT 7: SLPSTOPB[3:0]: Slope Stop B Signal Selection
117  ||||||||| _______ BIT 6:
118  |||||||||| ______ BIT 5:
119  ||||||||||| _____ BIT 4:
120  |||||||||||| ____ BIT 3: SLPSTRT[3:0]: Slope Start Signal Selection
121  ||||||||||||| ___ BIT 2:
122  |||||||||||||| __ BIT 1:
123  ||||||||||||||| _ BIT 0:
124  |||||||||||||||| */
125 #define REG_SLPxCONL 0b0000000000000000
126 
131 /*
132 
133  ________________ BIT 15: SLOPEN: Slope Function Enable/On
134  | _______________ BIT 14: (unimplemented)
135  || ______________ BIT 13: (unimplemented)
136  ||| _____________ BIT 12: (unimplemented)
137  |||| ____________ BIT 11: HME: Hysteretic Mode Enable bit
138  ||||| ___________ BIT 10: TWME: Triangle Wave Mode Enable
139  |||||| __________ BIT 9: PSE: Positive Slope Mode Enable
140  ||||||| _________ BIT 8: (unimplemented)
141  |||||||| ________ BIT 7: (unimplemented)
142  ||||||||| _______ BIT 6: (unimplemented)
143  |||||||||| ______ BIT 5: (unimplemented)
144  ||||||||||| _____ BIT 4: (unimplemented)
145  |||||||||||| ____ BIT 3: (unimplemented)
146  ||||||||||||| ___ BIT 2: (unimplemented)
147  |||||||||||||| __ BIT 1: (unimplemented)
148  ||||||||||||||| _ BIT 0: (unimplemented)
149  |||||||||||||||| */
150 #define REG_SLPxCONH_PC 0b1000000000000000 // Peak Current Mode Configuration
151 #define REG_SLPxCONH 0b0000000000000000 // Slope COmpensation disabled
152 
157 /*
158  ________________ BIT 15: DACON: Slope Function Enable bit
159  | _______________ BIT 14: (unimplemented)
160  || ______________ BIT 13: DACSIDL: DAC Stop in Idle Mode bit
161  ||| _____________ BIT 12: (unimplemented)
162  |||| ____________ BIT 11: (unimplemented)
163  ||||| ___________ BIT 10: (unimplemented)
164  |||||| __________ BIT 9: (unimplemented)
165  ||||||| _________ BIT 8: (unimplemented)
166  |||||||| ________ BIT 7: CLKSEL[1:0]: DAC Clock Source Select bits
167  ||||||||| _______ BIT 6:
168  |||||||||| ______ BIT 5: CLKDIV[1:0]: DAC Clock Divider bits
169  ||||||||||| _____ BIT 4:
170  |||||||||||| ____ BIT 3: (unimplemented)
171  ||||||||||||| ___ BIT 2: FCLKDIV[2:0]: Comparator Filter Clock Divider bits
172  |||||||||||||| __ BIT 1:
173  ||||||||||||||| _ BIT 0:
174  |||||||||||||||| */
175 #define REG_DACCTRL1L 0b0000000010000000 // Selecting AFPLLO as default input clock with no dividers
176 
181 /*
182  ________________ BIT 15: (unimplemented)
183  | _______________ BIT 14: (unimplemented)
184  || ______________ BIT 13: (unimplemented)
185  ||| _____________ BIT 12: (unimplemented)
186  |||| ____________ BIT 11: (unimplemented)
187  ||||| ___________ BIT 10: (unimplemented)
188  |||||| __________ BIT 9: TMODTIME[9:0]: Transition Mode Duration bits
189  ||||||| _________ BIT 8:
190  |||||||| ________ BIT 7:
191  ||||||||| _______ BIT 6:
192  |||||||||| ______ BIT 5:
193  ||||||||||| _____ BIT 4:
194  |||||||||||| ____ BIT 3:
195  ||||||||||||| ___ BIT 2:
196  |||||||||||||| __ BIT 1:
197  ||||||||||||||| _ BIT 0:
198  |||||||||||||||| */
199 #define REG_DACCTRL2L 0b0000000000000000 // Transition time setting will be loaded during initializaiton
200 
205 /*
206  ________________ BIT 15: (unimplemented)
207  | _______________ BIT 14: (unimplemented)
208  || ______________ BIT 13: (unimplemented)
209  ||| _____________ BIT 12: (unimplemented)
210  |||| ____________ BIT 11: (unimplemented)
211  ||||| ___________ BIT 10: (unimplemented)
212  |||||| __________ BIT 9: SSTIME[9:0]: Time from Start of Transition Mode until Steady-State Filter is Enabled bits
213  ||||||| _________ BIT 8:
214  |||||||| ________ BIT 7:
215  ||||||||| _______ BIT 6:
216  |||||||||| ______ BIT 5:
217  ||||||||||| _____ BIT 4:
218  |||||||||||| ____ BIT 3:
219  ||||||||||||| ___ BIT 2:
220  |||||||||||||| __ BIT 1:
221  ||||||||||||||| _ BIT 0:
222  |||||||||||||||| */
223 #define REG_DACCTRL2H 0b0000000000000000 // Steady-State time setting will be loaded during initializaiton
224 
225 
226 /* ********************************************************************************
227  * PUBLIC DATA OBJECTS
228  * *******************************************************************************/
229 extern volatile struct P33C_DAC_MODULE_s buckDacModuleConfig;
230 extern volatile struct P33C_DAC_INSTANCE_s buckDacInstanceConfig;
231 
232 
235 #endif /* BUCK_CONVERTER_PERIPHERAL_CONFIGURATION_DAC_H */
buckDacInstanceConfig
volatile struct P33C_DAC_INSTANCE_s buckDacInstanceConfig
DAC generator default configuration.
Definition: dev_buck_ptemp_dac.c:29
buckDacModuleConfig
volatile struct P33C_DAC_MODULE_s buckDacModuleConfig
DAC module default configuration.
Definition: dev_buck_ptemp_dac.c:16
P33C_DAC_MODULE_s
Abstracted set of Special Function Registers of a Digital-to-Analog Converter peripheral.
Definition: p33c_dac.h:60