Firmware Architecture

Firmware Flowchart. More...

Collaboration diagram for Firmware Architecture:

Modules
	Device Start Up
	Device Start Up.
	Main Loop
	Main Loop.

Detailed Description

Firmware Flowchart.

Firmware Task Scheduling

The SMPS Firmware Framework used in this application is organizing high and low priority tasks by a very simple task scheduler providing one common low-priority task level executed on priority level #0 and one high-priority task level executed on priority level #2. The interruption of processes on priority level #0 is enforced by a programmable timer. During system startup, the timer is set to overrun every 100 us, providing a stable high-priority task execution frequency of 10 kHz. All low-priority tasks are only allowed to run after all high-priority tasks have been completed. The real-time control system takes the highest priority within the firmware. This is ensured by using hardware triggers generated by the PWM signal generator logic with its high resolution time-base. The extremely short and optimized control loop code is implemented as monolithic Assembly routine to be most deterministic. Being triggered directly by the switching signal waveform generator, the execution is tightly coupled to the physical power conversion process and also independent from any other software process of the firmware.